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Update file_organization.rst

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docs/source/fpga_verilog/file_organization.rst
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@ -8,6 +8,8 @@ All the generated Verilog Netlists are located in the <verilog_dir> as you speci
:widths: 10, 20
"name_top.v", "Contains the top module and calls all the other .v files"
"name.bitstream", "Only if --fpga_verilog_print_top_testbench or --fpga_verilog_print_top_auto_testbench is chosen. Contains the bitstream programming the generated FPGA."
"name_top_tb.v", "Only if --fpga_verilog_print_top_testbench or --fpga_verilog_print_top_auto_testbench is chosen. Contains the testbench used for the simulation."
"lb", "Logic Block. Contains all the CLBs. The logic_block.v includes all the CLB and is called by the top module afterward"
"routing", "Contains all the routing in the circuit. You can find in it the Switch Boxes, the Connection Blocks and the routing needed to connect the different blocks together. The routing.v file packs them all and is called by the top module"
"sub_modules", "Contains the modules generated by the flow to build the CLBs"