From ba303450e2041321cef7b810e09c05acc68ea134 Mon Sep 17 00:00:00 2001 From: LNIS-Projects <40280375+LNIS-Projects@users.noreply.github.com> Date: Sat, 22 Dec 2018 14:45:00 +0100 Subject: [PATCH] Update file_organization.rst --- docs/source/fpga_verilog/file_organization.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/source/fpga_verilog/file_organization.rst b/docs/source/fpga_verilog/file_organization.rst index f4a0298e0..bfbf3a37f 100644 --- a/docs/source/fpga_verilog/file_organization.rst +++ b/docs/source/fpga_verilog/file_organization.rst @@ -8,6 +8,8 @@ All the generated Verilog Netlists are located in the as you speci :widths: 10, 20 "name_top.v", "Contains the top module and calls all the other .v files" + "name.bitstream", "Only if --fpga_verilog_print_top_testbench or --fpga_verilog_print_top_auto_testbench is chosen. Contains the bitstream programming the generated FPGA." + "name_top_tb.v", "Only if --fpga_verilog_print_top_testbench or --fpga_verilog_print_top_auto_testbench is chosen. Contains the testbench used for the simulation." "lb", "Logic Block. Contains all the CLBs. The logic_block.v includes all the CLB and is called by the top module afterward" "routing", "Contains all the routing in the circuit. You can find in it the Switch Boxes, the Connection Blocks and the routing needed to connect the different blocks together. The routing.v file packs them all and is called by the top module" "sub_modules", "Contains the modules generated by the flow to build the CLBs"