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[Doc] Update doc about big endian syntax in bus group file format

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tangxifan 2022-02-18 23:07:18 -08:00
parent 671188dfa4
commit b78e58d9bf
1 changed files with 5 additions and 1 deletions
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6
docs/source/manual/file_formats/bus_group_file.rst
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@ -13,7 +13,7 @@ An example of file is shown as follows.
.. code-block:: xml
<bus_group>
<bus name="i_addr[0:3]">
<bus name="i_addr[0:3]" big_endian="false">
<pin id="0" name="i_addr_0_"/>
<pin id="1" name="i_addr_1_"/>
<pin id="2" name="i_addr_2_"/>
@ -28,6 +28,10 @@ Bus-related Syntax
The bus port defined before synthesis, e.g., addr[0:3]
.. option:: big_endian="<bool>"
Specify if this port should follow big endian or little endian in Verilog netlist. By default, big endian is assumed, e.g., addr[0:3].
Pin-related Syntax
------------------