From b78e58d9bfcefff7574c572f52d33085156e7de2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 18 Feb 2022 23:07:18 -0800
Subject: [PATCH] [Doc] Update doc about big endian syntax in bus group file
 format

---
 docs/source/manual/file_formats/bus_group_file.rst | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/docs/source/manual/file_formats/bus_group_file.rst b/docs/source/manual/file_formats/bus_group_file.rst
index bf14fec4e..8faf0ffb7 100644
--- a/docs/source/manual/file_formats/bus_group_file.rst
+++ b/docs/source/manual/file_formats/bus_group_file.rst
@@ -13,7 +13,7 @@ An example of file is shown as follows.
 .. code-block:: xml
 
   <bus_group>
-    <bus name="i_addr[0:3]">
+    <bus name="i_addr[0:3]" big_endian="false">
       <pin id="0" name="i_addr_0_"/>
       <pin id="1" name="i_addr_1_"/>
       <pin id="2" name="i_addr_2_"/>
@@ -28,6 +28,10 @@ Bus-related Syntax
 
   The bus port defined before synthesis, e.g., addr[0:3]
 
+.. option:: big_endian="<bool>"
+
+  Specify if this port should follow big endian or little endian in Verilog netlist. By default, big endian is assumed, e.g., addr[0:3].
+
 Pin-related Syntax
 ------------------