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[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed

This commit is contained in:
tangxifan 2022-09-20 14:14:18 -07:00
parent abee802830
commit b630d60b7e
4 changed files with 516 additions and 508 deletions
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6
openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm.place Normal file
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@ -0,0 +1,6 @@
#block name x y subblk block number
#---------- -- -- ------ ------------
c 2 2 0 #0
out:c 3 2 6 #1
a 3 2 0 #2
b 3 2 4 #3

1014
openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml
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File diff suppressed because it is too large Load Diff

2
openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga
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@ -1,6 +1,6 @@
# Run VPR for the 'and' design # Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml #--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --fix_clusters ${OPENFPGA_VPR_FIX_CLUSTERS} --skip_sync_clustering_and_routing_results on
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
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@ -21,6 +21,8 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml
openfpga_vpr_device_layout=2x2 openfpga_vpr_device_layout=2x2
openfpga_vpr_route_chan_width=18
openfpga_vpr_fix_clusters=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm.place
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml