From b630d60b7e7426e93a3c9c283562f311ec20cfe5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 20 Sep 2022 14:14:18 -0700
Subject: [PATCH] [test] update arch bitstream and force a pin placement for
 the test case where external bistream is fixed

---
 .../and2_k4_N4_tileable_40nm.place            |    6 +
 .../and2_k4_N4_tileable_40nm_bitstream.xml    | 1014 ++++++++---------
 ...nal_arch_bitstream_example_script.openfpga |    2 +-
 .../config/task.conf                          |    2 +
 4 files changed, 516 insertions(+), 508 deletions(-)
 create mode 100644 openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm.place

diff --git a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm.place b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm.place
new file mode 100644
index 000000000..0cfd90a03
--- /dev/null
+++ b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm.place
@@ -0,0 +1,6 @@
+#block name	x	y	subblk	block number
+#----------	--	--	------	------------
+c		2	2	0	#0
+out:c		3	2	6	#1
+a		3	2	0	#2
+b		3	2	4	#3
diff --git a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml
index 28d1265f6..41365fca1 100644
--- a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml
+++ b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml
@@ -2,7 +2,7 @@
 	- Architecture independent bitstream
 	- Author: Xifan TANG
 	- Organization: University of Utah
-	- Date: Fri Sep 25 21:30:07 2020
+	- Date: Tue Sep 20 14:06:47 2022
 -->
 
 <bitstream_block name="fpga_top" hierarchy_level="0">
@@ -1285,13 +1285,13 @@
 								<instance level="6" name="lut4_LATCHR_mem"/>
 							</hierarchy>
 							<bitstream>
-								<bit memory_port="mem_out[0]" value="1"/>
+								<bit memory_port="mem_out[0]" value="0"/>
 								<bit memory_port="mem_out[1]" value="0"/>
-								<bit memory_port="mem_out[2]" value="1"/>
+								<bit memory_port="mem_out[2]" value="0"/>
 								<bit memory_port="mem_out[3]" value="0"/>
-								<bit memory_port="mem_out[4]" value="1"/>
+								<bit memory_port="mem_out[4]" value="0"/>
 								<bit memory_port="mem_out[5]" value="0"/>
-								<bit memory_port="mem_out[6]" value="1"/>
+								<bit memory_port="mem_out[6]" value="0"/>
 								<bit memory_port="mem_out[7]" value="0"/>
 								<bit memory_port="mem_out[8]" value="0"/>
 								<bit memory_port="mem_out[9]" value="0"/>
@@ -1313,17 +1313,13 @@
 							<instance level="4" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0"/>
 							<instance level="5" name="mem_ble4_out_0"/>
 						</hierarchy>
-						<input_nets>
-							<path id="0" net_name="unmapped"/>
-							<path id="1" net_name="c"/>
-						</input_nets>
 						<output_nets>
-							<path id="0" net_name="c"/>
+							<path id="0" net_name="unmapped"/>
 						</output_nets>
-						<bitstream path_id="1">
+						<bitstream path_id="-1">
 							<bit memory_port="mem_out[0]" value="0"/>
-							<bit memory_port="mem_out[1]" value="1"/>
-							<bit memory_port="mem_out[2]" value="0"/>
+							<bit memory_port="mem_out[1]" value="0"/>
+							<bit memory_port="mem_out[2]" value="1"/>
 						</bitstream>
 					</bitstream_block>
 				</bitstream_block>
@@ -1587,34 +1583,18 @@
 					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
 					<instance level="3" name="mem_fle_3_in_0"/>
 				</hierarchy>
-				<input_nets>
-					<path id="0" net_name="a"/>
-					<path id="1" net_name="unmapped"/>
-					<path id="2" net_name="unmapped"/>
-					<path id="3" net_name="unmapped"/>
-					<path id="4" net_name="unmapped"/>
-					<path id="5" net_name="unmapped"/>
-					<path id="6" net_name="b"/>
-					<path id="7" net_name="unmapped"/>
-					<path id="8" net_name="unmapped"/>
-					<path id="9" net_name="unmapped"/>
-					<path id="10" net_name="unmapped"/>
-					<path id="11" net_name="unmapped"/>
-					<path id="12" net_name="unmapped"/>
-					<path id="13" net_name="c"/>
-				</input_nets>
 				<output_nets>
-					<path id="0" net_name="b"/>
+					<path id="0" net_name="unmapped"/>
 				</output_nets>
-				<bitstream path_id="6">
+				<bitstream path_id="-1">
 					<bit memory_port="mem_out[0]" value="0"/>
 					<bit memory_port="mem_out[1]" value="0"/>
 					<bit memory_port="mem_out[2]" value="1"/>
 					<bit memory_port="mem_out[3]" value="0"/>
 					<bit memory_port="mem_out[4]" value="0"/>
-					<bit memory_port="mem_out[5]" value="1"/>
+					<bit memory_port="mem_out[5]" value="0"/>
 					<bit memory_port="mem_out[6]" value="0"/>
-					<bit memory_port="mem_out[7]" value="0"/>
+					<bit memory_port="mem_out[7]" value="1"/>
 				</bitstream>
 			</bitstream_block>
 			<bitstream_block name="mem_fle_3_in_1" hierarchy_level="3">
@@ -1666,34 +1646,18 @@
 					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
 					<instance level="3" name="mem_fle_3_in_3"/>
 				</hierarchy>
-				<input_nets>
-					<path id="0" net_name="a"/>
-					<path id="1" net_name="unmapped"/>
-					<path id="2" net_name="unmapped"/>
-					<path id="3" net_name="unmapped"/>
-					<path id="4" net_name="unmapped"/>
-					<path id="5" net_name="unmapped"/>
-					<path id="6" net_name="b"/>
-					<path id="7" net_name="unmapped"/>
-					<path id="8" net_name="unmapped"/>
-					<path id="9" net_name="unmapped"/>
-					<path id="10" net_name="unmapped"/>
-					<path id="11" net_name="unmapped"/>
-					<path id="12" net_name="unmapped"/>
-					<path id="13" net_name="c"/>
-				</input_nets>
 				<output_nets>
-					<path id="0" net_name="a"/>
+					<path id="0" net_name="unmapped"/>
 				</output_nets>
-				<bitstream path_id="0">
-					<bit memory_port="mem_out[0]" value="1"/>
+				<bitstream path_id="-1">
+					<bit memory_port="mem_out[0]" value="0"/>
 					<bit memory_port="mem_out[1]" value="0"/>
-					<bit memory_port="mem_out[2]" value="0"/>
+					<bit memory_port="mem_out[2]" value="1"/>
 					<bit memory_port="mem_out[3]" value="0"/>
-					<bit memory_port="mem_out[4]" value="1"/>
+					<bit memory_port="mem_out[4]" value="0"/>
 					<bit memory_port="mem_out[5]" value="0"/>
 					<bit memory_port="mem_out[6]" value="0"/>
-					<bit memory_port="mem_out[7]" value="0"/>
+					<bit memory_port="mem_out[7]" value="1"/>
 				</bitstream>
 			</bitstream_block>
 		</bitstream_block>
@@ -1873,13 +1837,13 @@
 								<instance level="6" name="lut4_LATCHR_mem"/>
 							</hierarchy>
 							<bitstream>
-								<bit memory_port="mem_out[0]" value="0"/>
+								<bit memory_port="mem_out[0]" value="1"/>
 								<bit memory_port="mem_out[1]" value="0"/>
-								<bit memory_port="mem_out[2]" value="0"/>
+								<bit memory_port="mem_out[2]" value="1"/>
 								<bit memory_port="mem_out[3]" value="0"/>
-								<bit memory_port="mem_out[4]" value="0"/>
+								<bit memory_port="mem_out[4]" value="1"/>
 								<bit memory_port="mem_out[5]" value="0"/>
-								<bit memory_port="mem_out[6]" value="0"/>
+								<bit memory_port="mem_out[6]" value="1"/>
 								<bit memory_port="mem_out[7]" value="0"/>
 								<bit memory_port="mem_out[8]" value="0"/>
 								<bit memory_port="mem_out[9]" value="0"/>
@@ -1901,13 +1865,17 @@
 							<instance level="4" name="logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_0"/>
 							<instance level="5" name="mem_ble4_out_0"/>
 						</hierarchy>
-						<output_nets>
+						<input_nets>
 							<path id="0" net_name="unmapped"/>
+							<path id="1" net_name="c"/>
+						</input_nets>
+						<output_nets>
+							<path id="0" net_name="c"/>
 						</output_nets>
-						<bitstream path_id="-1">
+						<bitstream path_id="1">
 							<bit memory_port="mem_out[0]" value="0"/>
-							<bit memory_port="mem_out[1]" value="0"/>
-							<bit memory_port="mem_out[2]" value="1"/>
+							<bit memory_port="mem_out[1]" value="1"/>
+							<bit memory_port="mem_out[2]" value="0"/>
 						</bitstream>
 					</bitstream_block>
 				</bitstream_block>
@@ -2171,18 +2139,34 @@
 					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
 					<instance level="3" name="mem_fle_3_in_0"/>
 				</hierarchy>
-				<output_nets>
+				<input_nets>
 					<path id="0" net_name="unmapped"/>
+					<path id="1" net_name="b"/>
+					<path id="2" net_name="unmapped"/>
+					<path id="3" net_name="unmapped"/>
+					<path id="4" net_name="unmapped"/>
+					<path id="5" net_name="a"/>
+					<path id="6" net_name="unmapped"/>
+					<path id="7" net_name="unmapped"/>
+					<path id="8" net_name="unmapped"/>
+					<path id="9" net_name="unmapped"/>
+					<path id="10" net_name="unmapped"/>
+					<path id="11" net_name="unmapped"/>
+					<path id="12" net_name="unmapped"/>
+					<path id="13" net_name="c"/>
+				</input_nets>
+				<output_nets>
+					<path id="0" net_name="a"/>
 				</output_nets>
-				<bitstream path_id="-1">
+				<bitstream path_id="5">
 					<bit memory_port="mem_out[0]" value="0"/>
-					<bit memory_port="mem_out[1]" value="0"/>
-					<bit memory_port="mem_out[2]" value="1"/>
+					<bit memory_port="mem_out[1]" value="1"/>
+					<bit memory_port="mem_out[2]" value="0"/>
 					<bit memory_port="mem_out[3]" value="0"/>
 					<bit memory_port="mem_out[4]" value="0"/>
-					<bit memory_port="mem_out[5]" value="0"/>
+					<bit memory_port="mem_out[5]" value="1"/>
 					<bit memory_port="mem_out[6]" value="0"/>
-					<bit memory_port="mem_out[7]" value="1"/>
+					<bit memory_port="mem_out[7]" value="0"/>
 				</bitstream>
 			</bitstream_block>
 			<bitstream_block name="mem_fle_3_in_1" hierarchy_level="3">
@@ -2234,18 +2218,34 @@
 					<instance level="2" name="logical_tile_clb_mode_clb__0"/>
 					<instance level="3" name="mem_fle_3_in_3"/>
 				</hierarchy>
-				<output_nets>
+				<input_nets>
 					<path id="0" net_name="unmapped"/>
+					<path id="1" net_name="b"/>
+					<path id="2" net_name="unmapped"/>
+					<path id="3" net_name="unmapped"/>
+					<path id="4" net_name="unmapped"/>
+					<path id="5" net_name="a"/>
+					<path id="6" net_name="unmapped"/>
+					<path id="7" net_name="unmapped"/>
+					<path id="8" net_name="unmapped"/>
+					<path id="9" net_name="unmapped"/>
+					<path id="10" net_name="unmapped"/>
+					<path id="11" net_name="unmapped"/>
+					<path id="12" net_name="unmapped"/>
+					<path id="13" net_name="c"/>
+				</input_nets>
+				<output_nets>
+					<path id="0" net_name="b"/>
 				</output_nets>
-				<bitstream path_id="-1">
+				<bitstream path_id="1">
 					<bit memory_port="mem_out[0]" value="0"/>
-					<bit memory_port="mem_out[1]" value="0"/>
-					<bit memory_port="mem_out[2]" value="1"/>
+					<bit memory_port="mem_out[1]" value="1"/>
+					<bit memory_port="mem_out[2]" value="0"/>
 					<bit memory_port="mem_out[3]" value="0"/>
-					<bit memory_port="mem_out[4]" value="0"/>
+					<bit memory_port="mem_out[4]" value="1"/>
 					<bit memory_port="mem_out[5]" value="0"/>
 					<bit memory_port="mem_out[6]" value="0"/>
-					<bit memory_port="mem_out[7]" value="1"/>
+					<bit memory_port="mem_out[7]" value="0"/>
 				</bitstream>
 			</bitstream_block>
 		</bitstream_block>
@@ -2510,6 +2510,136 @@
 			</bitstream_block>
 		</bitstream_block>
 	</bitstream_block>
+	<bitstream_block name="grid_io_right_3__2_" hierarchy_level="1">
+		<bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
+			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
+				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
+					<hierarchy>
+						<instance level="0" name="fpga_top"/>
+						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="2" name="logical_tile_io_mode_io__0"/>
+						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
+						<instance level="4" name="GPIO_LATCHR_mem"/>
+					</hierarchy>
+					<bitstream>
+						<bit memory_port="mem_out[0]" value="1"/>
+					</bitstream>
+				</bitstream_block>
+			</bitstream_block>
+		</bitstream_block>
+		<bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
+			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
+				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
+					<hierarchy>
+						<instance level="0" name="fpga_top"/>
+						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="2" name="logical_tile_io_mode_io__1"/>
+						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
+						<instance level="4" name="GPIO_LATCHR_mem"/>
+					</hierarchy>
+					<bitstream>
+						<bit memory_port="mem_out[0]" value="1"/>
+					</bitstream>
+				</bitstream_block>
+			</bitstream_block>
+		</bitstream_block>
+		<bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
+			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
+				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
+					<hierarchy>
+						<instance level="0" name="fpga_top"/>
+						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="2" name="logical_tile_io_mode_io__2"/>
+						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
+						<instance level="4" name="GPIO_LATCHR_mem"/>
+					</hierarchy>
+					<bitstream>
+						<bit memory_port="mem_out[0]" value="1"/>
+					</bitstream>
+				</bitstream_block>
+			</bitstream_block>
+		</bitstream_block>
+		<bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
+			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
+				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
+					<hierarchy>
+						<instance level="0" name="fpga_top"/>
+						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="2" name="logical_tile_io_mode_io__3"/>
+						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
+						<instance level="4" name="GPIO_LATCHR_mem"/>
+					</hierarchy>
+					<bitstream>
+						<bit memory_port="mem_out[0]" value="1"/>
+					</bitstream>
+				</bitstream_block>
+			</bitstream_block>
+		</bitstream_block>
+		<bitstream_block name="logical_tile_io_mode_io__4" hierarchy_level="2">
+			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
+				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
+					<hierarchy>
+						<instance level="0" name="fpga_top"/>
+						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="2" name="logical_tile_io_mode_io__4"/>
+						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
+						<instance level="4" name="GPIO_LATCHR_mem"/>
+					</hierarchy>
+					<bitstream>
+						<bit memory_port="mem_out[0]" value="1"/>
+					</bitstream>
+				</bitstream_block>
+			</bitstream_block>
+		</bitstream_block>
+		<bitstream_block name="logical_tile_io_mode_io__5" hierarchy_level="2">
+			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
+				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
+					<hierarchy>
+						<instance level="0" name="fpga_top"/>
+						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="2" name="logical_tile_io_mode_io__5"/>
+						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
+						<instance level="4" name="GPIO_LATCHR_mem"/>
+					</hierarchy>
+					<bitstream>
+						<bit memory_port="mem_out[0]" value="1"/>
+					</bitstream>
+				</bitstream_block>
+			</bitstream_block>
+		</bitstream_block>
+		<bitstream_block name="logical_tile_io_mode_io__6" hierarchy_level="2">
+			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
+				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
+					<hierarchy>
+						<instance level="0" name="fpga_top"/>
+						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="2" name="logical_tile_io_mode_io__6"/>
+						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
+						<instance level="4" name="GPIO_LATCHR_mem"/>
+					</hierarchy>
+					<bitstream>
+						<bit memory_port="mem_out[0]" value="0"/>
+					</bitstream>
+				</bitstream_block>
+			</bitstream_block>
+		</bitstream_block>
+		<bitstream_block name="logical_tile_io_mode_io__7" hierarchy_level="2">
+			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
+				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
+					<hierarchy>
+						<instance level="0" name="fpga_top"/>
+						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="2" name="logical_tile_io_mode_io__7"/>
+						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
+						<instance level="4" name="GPIO_LATCHR_mem"/>
+					</hierarchy>
+					<bitstream>
+						<bit memory_port="mem_out[0]" value="1"/>
+					</bitstream>
+				</bitstream_block>
+			</bitstream_block>
+		</bitstream_block>
+	</bitstream_block>
 	<bitstream_block name="grid_io_right_3__1_" hierarchy_level="1">
 		<bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
 			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
@@ -2640,13 +2770,13 @@
 			</bitstream_block>
 		</bitstream_block>
 	</bitstream_block>
-	<bitstream_block name="grid_io_right_3__2_" hierarchy_level="1">
+	<bitstream_block name="grid_io_bottom_2__0_" hierarchy_level="1">
 		<bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
 			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
 				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
 					<hierarchy>
 						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="1" name="grid_io_bottom_2__0_"/>
 						<instance level="2" name="logical_tile_io_mode_io__0"/>
 						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
 						<instance level="4" name="GPIO_LATCHR_mem"/>
@@ -2662,7 +2792,7 @@
 				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
 					<hierarchy>
 						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="1" name="grid_io_bottom_2__0_"/>
 						<instance level="2" name="logical_tile_io_mode_io__1"/>
 						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
 						<instance level="4" name="GPIO_LATCHR_mem"/>
@@ -2678,7 +2808,7 @@
 				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
 					<hierarchy>
 						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="1" name="grid_io_bottom_2__0_"/>
 						<instance level="2" name="logical_tile_io_mode_io__2"/>
 						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
 						<instance level="4" name="GPIO_LATCHR_mem"/>
@@ -2694,7 +2824,7 @@
 				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
 					<hierarchy>
 						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="1" name="grid_io_bottom_2__0_"/>
 						<instance level="2" name="logical_tile_io_mode_io__3"/>
 						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
 						<instance level="4" name="GPIO_LATCHR_mem"/>
@@ -2710,7 +2840,7 @@
 				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
 					<hierarchy>
 						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="1" name="grid_io_bottom_2__0_"/>
 						<instance level="2" name="logical_tile_io_mode_io__4"/>
 						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
 						<instance level="4" name="GPIO_LATCHR_mem"/>
@@ -2726,7 +2856,7 @@
 				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
 					<hierarchy>
 						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="1" name="grid_io_bottom_2__0_"/>
 						<instance level="2" name="logical_tile_io_mode_io__5"/>
 						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
 						<instance level="4" name="GPIO_LATCHR_mem"/>
@@ -2742,7 +2872,7 @@
 				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
 					<hierarchy>
 						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="1" name="grid_io_bottom_2__0_"/>
 						<instance level="2" name="logical_tile_io_mode_io__6"/>
 						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
 						<instance level="4" name="GPIO_LATCHR_mem"/>
@@ -2758,7 +2888,7 @@
 				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
 					<hierarchy>
 						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_right_3__2_"/>
+						<instance level="1" name="grid_io_bottom_2__0_"/>
 						<instance level="2" name="logical_tile_io_mode_io__7"/>
 						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
 						<instance level="4" name="GPIO_LATCHR_mem"/>
@@ -2900,136 +3030,6 @@
 			</bitstream_block>
 		</bitstream_block>
 	</bitstream_block>
-	<bitstream_block name="grid_io_bottom_2__0_" hierarchy_level="1">
-		<bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
-			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
-					<hierarchy>
-						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_bottom_2__0_"/>
-						<instance level="2" name="logical_tile_io_mode_io__0"/>
-						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-						<instance level="4" name="GPIO_LATCHR_mem"/>
-					</hierarchy>
-					<bitstream>
-						<bit memory_port="mem_out[0]" value="1"/>
-					</bitstream>
-				</bitstream_block>
-			</bitstream_block>
-		</bitstream_block>
-		<bitstream_block name="logical_tile_io_mode_io__1" hierarchy_level="2">
-			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
-					<hierarchy>
-						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_bottom_2__0_"/>
-						<instance level="2" name="logical_tile_io_mode_io__1"/>
-						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-						<instance level="4" name="GPIO_LATCHR_mem"/>
-					</hierarchy>
-					<bitstream>
-						<bit memory_port="mem_out[0]" value="1"/>
-					</bitstream>
-				</bitstream_block>
-			</bitstream_block>
-		</bitstream_block>
-		<bitstream_block name="logical_tile_io_mode_io__2" hierarchy_level="2">
-			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
-					<hierarchy>
-						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_bottom_2__0_"/>
-						<instance level="2" name="logical_tile_io_mode_io__2"/>
-						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-						<instance level="4" name="GPIO_LATCHR_mem"/>
-					</hierarchy>
-					<bitstream>
-						<bit memory_port="mem_out[0]" value="1"/>
-					</bitstream>
-				</bitstream_block>
-			</bitstream_block>
-		</bitstream_block>
-		<bitstream_block name="logical_tile_io_mode_io__3" hierarchy_level="2">
-			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
-					<hierarchy>
-						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_bottom_2__0_"/>
-						<instance level="2" name="logical_tile_io_mode_io__3"/>
-						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-						<instance level="4" name="GPIO_LATCHR_mem"/>
-					</hierarchy>
-					<bitstream>
-						<bit memory_port="mem_out[0]" value="1"/>
-					</bitstream>
-				</bitstream_block>
-			</bitstream_block>
-		</bitstream_block>
-		<bitstream_block name="logical_tile_io_mode_io__4" hierarchy_level="2">
-			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
-					<hierarchy>
-						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_bottom_2__0_"/>
-						<instance level="2" name="logical_tile_io_mode_io__4"/>
-						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-						<instance level="4" name="GPIO_LATCHR_mem"/>
-					</hierarchy>
-					<bitstream>
-						<bit memory_port="mem_out[0]" value="1"/>
-					</bitstream>
-				</bitstream_block>
-			</bitstream_block>
-		</bitstream_block>
-		<bitstream_block name="logical_tile_io_mode_io__5" hierarchy_level="2">
-			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
-					<hierarchy>
-						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_bottom_2__0_"/>
-						<instance level="2" name="logical_tile_io_mode_io__5"/>
-						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-						<instance level="4" name="GPIO_LATCHR_mem"/>
-					</hierarchy>
-					<bitstream>
-						<bit memory_port="mem_out[0]" value="1"/>
-					</bitstream>
-				</bitstream_block>
-			</bitstream_block>
-		</bitstream_block>
-		<bitstream_block name="logical_tile_io_mode_io__6" hierarchy_level="2">
-			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
-					<hierarchy>
-						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_bottom_2__0_"/>
-						<instance level="2" name="logical_tile_io_mode_io__6"/>
-						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-						<instance level="4" name="GPIO_LATCHR_mem"/>
-					</hierarchy>
-					<bitstream>
-						<bit memory_port="mem_out[0]" value="0"/>
-					</bitstream>
-				</bitstream_block>
-			</bitstream_block>
-		</bitstream_block>
-		<bitstream_block name="logical_tile_io_mode_io__7" hierarchy_level="2">
-			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
-				<bitstream_block name="GPIO_LATCHR_mem" hierarchy_level="4">
-					<hierarchy>
-						<instance level="0" name="fpga_top"/>
-						<instance level="1" name="grid_io_bottom_2__0_"/>
-						<instance level="2" name="logical_tile_io_mode_io__7"/>
-						<instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-						<instance level="4" name="GPIO_LATCHR_mem"/>
-					</hierarchy>
-					<bitstream>
-						<bit memory_port="mem_out[0]" value="1"/>
-					</bitstream>
-				</bitstream_block>
-			</bitstream_block>
-		</bitstream_block>
-	</bitstream_block>
 	<bitstream_block name="grid_io_left_0__1_" hierarchy_level="1">
 		<bitstream_block name="logical_tile_io_mode_io__0" hierarchy_level="2">
 			<bitstream_block name="logical_tile_io_mode_physical__iopad_0" hierarchy_level="3">
@@ -3317,7 +3317,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="b"/>
+				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
 				<path id="0" net_name="unmapped"/>
@@ -3655,7 +3655,7 @@
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="c"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 				<path id="6" net_name="unmapped"/>
@@ -3897,7 +3897,7 @@
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="c"/>
+				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
@@ -4252,7 +4252,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="b"/>
+				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
@@ -4386,7 +4386,7 @@
 				<path id="0" net_name="c"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="b"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 				<path id="6" net_name="unmapped"/>
@@ -4470,7 +4470,7 @@
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="b"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 				<path id="6" net_name="unmapped"/>
@@ -4526,9 +4526,9 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="c"/>
+				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="unmapped"/>
+				<path id="3" net_name="c"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 				<path id="6" net_name="unmapped"/>
@@ -4588,7 +4588,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="a"/>
+				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
@@ -4707,9 +4707,9 @@
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="c"/>
+				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="unmapped"/>
+				<path id="4" net_name="c"/>
 				<path id="5" net_name="unmapped"/>
 				<path id="6" net_name="unmapped"/>
 				<path id="7" net_name="unmapped"/>
@@ -4718,13 +4718,13 @@
 			<output_nets>
 				<path id="0" net_name="c"/>
 			</output_nets>
-			<bitstream path_id="2">
-				<bit memory_port="mem_out[0]" value="0"/>
+			<bitstream path_id="4">
+				<bit memory_port="mem_out[0]" value="1"/>
 				<bit memory_port="mem_out[1]" value="0"/>
-				<bit memory_port="mem_out[2]" value="1"/>
+				<bit memory_port="mem_out[2]" value="0"/>
 				<bit memory_port="mem_out[3]" value="0"/>
-				<bit memory_port="mem_out[4]" value="1"/>
-				<bit memory_port="mem_out[5]" value="0"/>
+				<bit memory_port="mem_out[4]" value="0"/>
+				<bit memory_port="mem_out[5]" value="1"/>
 				<bit memory_port="mem_out[6]" value="0"/>
 				<bit memory_port="mem_out[7]" value="0"/>
 			</bitstream>
@@ -4739,7 +4739,7 @@
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="a"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 				<path id="6" net_name="unmapped"/>
@@ -4829,7 +4829,7 @@
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="c"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 				<path id="6" net_name="unmapped"/>
@@ -5221,15 +5221,15 @@
 				<instance level="2" name="mem_top_track_0"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
-				<bit memory_port="mem_out[0]" value="1"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+			<bitstream path_id="-1">
+				<bit memory_port="mem_out[0]" value="0"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_top_track_2" hierarchy_level="2">
@@ -5257,15 +5257,15 @@
 				<instance level="2" name="mem_top_track_4"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="a"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="a"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
-				<bit memory_port="mem_out[0]" value="1"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+			<bitstream path_id="-1">
+				<bit memory_port="mem_out[0]" value="0"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_top_track_6" hierarchy_level="2">
@@ -5315,11 +5315,11 @@
 				<path id="1" net_name="c"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="c"/>
 			</output_nets>
-			<bitstream path_id="-1">
+			<bitstream path_id="1">
 				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="0"/>
+				<bit memory_port="mem_out[1]" value="1"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_top_track_12" hierarchy_level="2">
@@ -5402,14 +5402,14 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="b"/>
+				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="b"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="1">
+			<bitstream path_id="-1">
 				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_left_track_5" hierarchy_level="2">
@@ -5527,7 +5527,7 @@
 				<instance level="2" name="mem_left_track_17"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="a"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -5547,10 +5547,10 @@
 				<instance level="2" name="mem_top_track_0"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="c"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="c"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 				<path id="6" net_name="unmapped"/>
@@ -5575,11 +5575,11 @@
 				<instance level="2" name="mem_top_track_8"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="a"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="unmapped"/>
+				<path id="4" net_name="c"/>
 				<path id="5" net_name="unmapped"/>
 				<path id="6" net_name="unmapped"/>
 				<path id="7" net_name="unmapped"/>
@@ -5604,24 +5604,24 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="unmapped"/>
+				<path id="1" net_name="b"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="a"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 				<path id="6" net_name="unmapped"/>
 				<path id="7" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="b"/>
 			</output_nets>
-			<bitstream path_id="-1">
+			<bitstream path_id="1">
 				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="0"/>
-				<bit memory_port="mem_out[2]" value="1"/>
-				<bit memory_port="mem_out[3]" value="0"/>
+				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[2]" value="0"/>
+				<bit memory_port="mem_out[3]" value="1"/>
 				<bit memory_port="mem_out[4]" value="0"/>
-				<bit memory_port="mem_out[5]" value="1"/>
+				<bit memory_port="mem_out[5]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_bottom_track_1" hierarchy_level="2">
@@ -5631,7 +5631,7 @@
 				<instance level="2" name="mem_bottom_track_1"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="a"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
@@ -5661,7 +5661,7 @@
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="a"/>
+				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
@@ -5691,7 +5691,7 @@
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="c"/>
+				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 				<path id="6" net_name="unmapped"/>
 				<path id="7" net_name="unmapped"/>
@@ -5715,7 +5715,7 @@
 				<instance level="2" name="mem_left_track_1"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="a"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 			</input_nets>
@@ -5734,16 +5734,16 @@
 				<instance level="2" name="mem_left_track_3"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
-				<bit memory_port="mem_out[0]" value="1"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+			<bitstream path_id="-1">
+				<bit memory_port="mem_out[0]" value="0"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_left_track_5" hierarchy_level="2">
@@ -5771,15 +5771,15 @@
 				<instance level="2" name="mem_left_track_7"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="a"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="a"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="0">
-				<bit memory_port="mem_out[0]" value="1"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+			<bitstream path_id="-1">
+				<bit memory_port="mem_out[0]" value="0"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_left_track_9" hierarchy_level="2">
@@ -5808,7 +5808,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="unmapped"/>
+				<path id="1" net_name="c"/>
 			</input_nets>
 			<output_nets>
 				<path id="0" net_name="unmapped"/>
@@ -5844,14 +5844,14 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="unmapped"/>
+				<path id="1" net_name="c"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="c"/>
 			</output_nets>
-			<bitstream path_id="-1">
+			<bitstream path_id="1">
 				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="0"/>
+				<bit memory_port="mem_out[1]" value="1"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_left_track_17" hierarchy_level="2">
@@ -5881,15 +5881,15 @@
 				<instance level="2" name="mem_bottom_track_1"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="a"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="a"/>
 			</output_nets>
-			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="0"/>
+			<bitstream path_id="0">
+				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[1]" value="1"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_bottom_track_3" hierarchy_level="2">
@@ -5953,7 +5953,7 @@
 				<instance level="2" name="mem_bottom_track_9"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="b"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -6025,15 +6025,15 @@
 				<instance level="2" name="mem_bottom_track_17"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="c"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="c"/>
 			</output_nets>
-			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="0"/>
+			<bitstream path_id="0">
+				<bit memory_port="mem_out[0]" value="1"/>
+				<bit memory_port="mem_out[1]" value="1"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_left_track_1" hierarchy_level="2">
@@ -6043,7 +6043,7 @@
 				<instance level="2" name="mem_left_track_1"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="b"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -6079,7 +6079,7 @@
 				<instance level="2" name="mem_left_track_5"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -6115,7 +6115,7 @@
 				<instance level="2" name="mem_left_track_9"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="a"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -6169,7 +6169,7 @@
 				<instance level="2" name="mem_left_track_15"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="c"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -6254,7 +6254,7 @@
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="b"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
@@ -6278,7 +6278,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="b"/>
+				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
@@ -6382,7 +6382,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="b"/>
+				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
@@ -6534,7 +6534,7 @@
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="c"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
@@ -6558,7 +6558,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="c"/>
+				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
@@ -6920,14 +6920,14 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="b"/>
+				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="b"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="1">
+			<bitstream path_id="-1">
 				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[1]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_bottom_ipin_2" hierarchy_level="2">
@@ -6938,7 +6938,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="b"/>
+				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
@@ -7042,7 +7042,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="b"/>
+				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
@@ -7127,15 +7127,15 @@
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="2">
+			<bitstream path_id="-1">
 				<bit memory_port="mem_out[0]" value="0"/>
 				<bit memory_port="mem_out[1]" value="0"/>
-				<bit memory_port="mem_out[2]" value="1"/>
-				<bit memory_port="mem_out[3]" value="1"/>
+				<bit memory_port="mem_out[2]" value="0"/>
+				<bit memory_port="mem_out[3]" value="0"/>
 				<bit memory_port="mem_out[4]" value="0"/>
-				<bit memory_port="mem_out[5]" value="0"/>
+				<bit memory_port="mem_out[5]" value="1"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_top_ipin_7" hierarchy_level="2">
@@ -7148,7 +7148,7 @@
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="b"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
@@ -7200,7 +7200,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="c"/>
+				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
 				<path id="0" net_name="unmapped"/>
@@ -7218,7 +7218,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="c"/>
+				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
@@ -7246,20 +7246,20 @@
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="a"/>
+				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="unmapped"/>
+				<path id="5" net_name="c"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="a"/>
+				<path id="0" net_name="unmapped"/>
 			</output_nets>
-			<bitstream path_id="3">
-				<bit memory_port="mem_out[0]" value="1"/>
+			<bitstream path_id="-1">
+				<bit memory_port="mem_out[0]" value="0"/>
 				<bit memory_port="mem_out[1]" value="0"/>
 				<bit memory_port="mem_out[2]" value="0"/>
 				<bit memory_port="mem_out[3]" value="0"/>
-				<bit memory_port="mem_out[4]" value="1"/>
-				<bit memory_port="mem_out[5]" value="0"/>
+				<bit memory_port="mem_out[4]" value="0"/>
+				<bit memory_port="mem_out[5]" value="1"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_top_ipin_1" hierarchy_level="2">
@@ -8303,7 +8303,7 @@
 				<instance level="2" name="mem_left_ipin_0"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
@@ -8329,11 +8329,11 @@
 				<instance level="2" name="mem_left_ipin_1"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="unmapped"/>
+				<path id="3" net_name="a"/>
+				<path id="4" net_name="c"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -8356,8 +8356,8 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="a"/>
+				<path id="1" net_name="a"/>
+				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
@@ -8381,7 +8381,7 @@
 				<instance level="2" name="mem_left_ipin_3"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="a"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
@@ -8433,11 +8433,11 @@
 				<instance level="2" name="mem_left_ipin_5"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="unmapped"/>
+				<path id="4" net_name="c"/>
 				<path id="5" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -8460,8 +8460,8 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="unmapped"/>
+				<path id="1" net_name="a"/>
+				<path id="2" net_name="c"/>
 				<path id="3" net_name="unmapped"/>
 				<path id="4" net_name="unmapped"/>
 				<path id="5" net_name="unmapped"/>
@@ -8485,7 +8485,7 @@
 				<instance level="2" name="mem_left_ipin_7"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="a"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
@@ -8537,7 +8537,7 @@
 				<instance level="2" name="mem_right_ipin_1"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
@@ -8556,7 +8556,7 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="unmapped"/>
+				<path id="1" net_name="a"/>
 			</input_nets>
 			<output_nets>
 				<path id="0" net_name="unmapped"/>
@@ -8574,6 +8574,84 @@
 				<instance level="1" name="cby_2__2_"/>
 				<instance level="2" name="mem_left_ipin_0"/>
 			</hierarchy>
+			<input_nets>
+				<path id="0" net_name="unmapped"/>
+				<path id="1" net_name="a"/>
+				<path id="2" net_name="unmapped"/>
+				<path id="3" net_name="unmapped"/>
+				<path id="4" net_name="b"/>
+				<path id="5" net_name="c"/>
+			</input_nets>
+			<output_nets>
+				<path id="0" net_name="unmapped"/>
+			</output_nets>
+			<bitstream path_id="-1">
+				<bit memory_port="mem_out[0]" value="0"/>
+				<bit memory_port="mem_out[1]" value="0"/>
+				<bit memory_port="mem_out[2]" value="0"/>
+				<bit memory_port="mem_out[3]" value="0"/>
+				<bit memory_port="mem_out[4]" value="0"/>
+				<bit memory_port="mem_out[5]" value="1"/>
+			</bitstream>
+		</bitstream_block>
+		<bitstream_block name="mem_left_ipin_1" hierarchy_level="2">
+			<hierarchy>
+				<instance level="0" name="fpga_top"/>
+				<instance level="1" name="cby_2__2_"/>
+				<instance level="2" name="mem_left_ipin_1"/>
+			</hierarchy>
+			<input_nets>
+				<path id="0" net_name="unmapped"/>
+				<path id="1" net_name="a"/>
+				<path id="2" net_name="unmapped"/>
+				<path id="3" net_name="unmapped"/>
+				<path id="4" net_name="unmapped"/>
+				<path id="5" net_name="unmapped"/>
+			</input_nets>
+			<output_nets>
+				<path id="0" net_name="unmapped"/>
+			</output_nets>
+			<bitstream path_id="-1">
+				<bit memory_port="mem_out[0]" value="0"/>
+				<bit memory_port="mem_out[1]" value="0"/>
+				<bit memory_port="mem_out[2]" value="0"/>
+				<bit memory_port="mem_out[3]" value="0"/>
+				<bit memory_port="mem_out[4]" value="0"/>
+				<bit memory_port="mem_out[5]" value="1"/>
+			</bitstream>
+		</bitstream_block>
+		<bitstream_block name="mem_left_ipin_2" hierarchy_level="2">
+			<hierarchy>
+				<instance level="0" name="fpga_top"/>
+				<instance level="1" name="cby_2__2_"/>
+				<instance level="2" name="mem_left_ipin_2"/>
+			</hierarchy>
+			<input_nets>
+				<path id="0" net_name="unmapped"/>
+				<path id="1" net_name="unmapped"/>
+				<path id="2" net_name="unmapped"/>
+				<path id="3" net_name="unmapped"/>
+				<path id="4" net_name="c"/>
+				<path id="5" net_name="unmapped"/>
+			</input_nets>
+			<output_nets>
+				<path id="0" net_name="unmapped"/>
+			</output_nets>
+			<bitstream path_id="-1">
+				<bit memory_port="mem_out[0]" value="0"/>
+				<bit memory_port="mem_out[1]" value="0"/>
+				<bit memory_port="mem_out[2]" value="0"/>
+				<bit memory_port="mem_out[3]" value="0"/>
+				<bit memory_port="mem_out[4]" value="0"/>
+				<bit memory_port="mem_out[5]" value="1"/>
+			</bitstream>
+		</bitstream_block>
+		<bitstream_block name="mem_left_ipin_3" hierarchy_level="2">
+			<hierarchy>
+				<instance level="0" name="fpga_top"/>
+				<instance level="1" name="cby_2__2_"/>
+				<instance level="2" name="mem_left_ipin_3"/>
+			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
@@ -8594,11 +8672,89 @@
 				<bit memory_port="mem_out[5]" value="1"/>
 			</bitstream>
 		</bitstream_block>
-		<bitstream_block name="mem_left_ipin_1" hierarchy_level="2">
+		<bitstream_block name="mem_left_ipin_4" hierarchy_level="2">
 			<hierarchy>
 				<instance level="0" name="fpga_top"/>
 				<instance level="1" name="cby_2__2_"/>
-				<instance level="2" name="mem_left_ipin_1"/>
+				<instance level="2" name="mem_left_ipin_4"/>
+			</hierarchy>
+			<input_nets>
+				<path id="0" net_name="unmapped"/>
+				<path id="1" net_name="unmapped"/>
+				<path id="2" net_name="unmapped"/>
+				<path id="3" net_name="unmapped"/>
+				<path id="4" net_name="b"/>
+				<path id="5" net_name="c"/>
+			</input_nets>
+			<output_nets>
+				<path id="0" net_name="unmapped"/>
+			</output_nets>
+			<bitstream path_id="-1">
+				<bit memory_port="mem_out[0]" value="0"/>
+				<bit memory_port="mem_out[1]" value="0"/>
+				<bit memory_port="mem_out[2]" value="0"/>
+				<bit memory_port="mem_out[3]" value="0"/>
+				<bit memory_port="mem_out[4]" value="0"/>
+				<bit memory_port="mem_out[5]" value="1"/>
+			</bitstream>
+		</bitstream_block>
+		<bitstream_block name="mem_left_ipin_5" hierarchy_level="2">
+			<hierarchy>
+				<instance level="0" name="fpga_top"/>
+				<instance level="1" name="cby_2__2_"/>
+				<instance level="2" name="mem_left_ipin_5"/>
+			</hierarchy>
+			<input_nets>
+				<path id="0" net_name="unmapped"/>
+				<path id="1" net_name="a"/>
+				<path id="2" net_name="unmapped"/>
+				<path id="3" net_name="unmapped"/>
+				<path id="4" net_name="unmapped"/>
+				<path id="5" net_name="unmapped"/>
+			</input_nets>
+			<output_nets>
+				<path id="0" net_name="unmapped"/>
+			</output_nets>
+			<bitstream path_id="-1">
+				<bit memory_port="mem_out[0]" value="0"/>
+				<bit memory_port="mem_out[1]" value="0"/>
+				<bit memory_port="mem_out[2]" value="0"/>
+				<bit memory_port="mem_out[3]" value="0"/>
+				<bit memory_port="mem_out[4]" value="0"/>
+				<bit memory_port="mem_out[5]" value="1"/>
+			</bitstream>
+		</bitstream_block>
+		<bitstream_block name="mem_left_ipin_6" hierarchy_level="2">
+			<hierarchy>
+				<instance level="0" name="fpga_top"/>
+				<instance level="1" name="cby_2__2_"/>
+				<instance level="2" name="mem_left_ipin_6"/>
+			</hierarchy>
+			<input_nets>
+				<path id="0" net_name="unmapped"/>
+				<path id="1" net_name="unmapped"/>
+				<path id="2" net_name="unmapped"/>
+				<path id="3" net_name="unmapped"/>
+				<path id="4" net_name="c"/>
+				<path id="5" net_name="unmapped"/>
+			</input_nets>
+			<output_nets>
+				<path id="0" net_name="c"/>
+			</output_nets>
+			<bitstream path_id="4">
+				<bit memory_port="mem_out[0]" value="0"/>
+				<bit memory_port="mem_out[1]" value="1"/>
+				<bit memory_port="mem_out[2]" value="0"/>
+				<bit memory_port="mem_out[3]" value="0"/>
+				<bit memory_port="mem_out[4]" value="1"/>
+				<bit memory_port="mem_out[5]" value="0"/>
+			</bitstream>
+		</bitstream_block>
+		<bitstream_block name="mem_left_ipin_7" hierarchy_level="2">
+			<hierarchy>
+				<instance level="0" name="fpga_top"/>
+				<instance level="1" name="cby_2__2_"/>
+				<instance level="2" name="mem_left_ipin_7"/>
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
@@ -8620,162 +8776,6 @@
 				<bit memory_port="mem_out[5]" value="1"/>
 			</bitstream>
 		</bitstream_block>
-		<bitstream_block name="mem_left_ipin_2" hierarchy_level="2">
-			<hierarchy>
-				<instance level="0" name="fpga_top"/>
-				<instance level="1" name="cby_2__2_"/>
-				<instance level="2" name="mem_left_ipin_2"/>
-			</hierarchy>
-			<input_nets>
-				<path id="0" net_name="c"/>
-				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="unmapped"/>
-			</input_nets>
-			<output_nets>
-				<path id="0" net_name="unmapped"/>
-			</output_nets>
-			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="0"/>
-				<bit memory_port="mem_out[2]" value="0"/>
-				<bit memory_port="mem_out[3]" value="0"/>
-				<bit memory_port="mem_out[4]" value="0"/>
-				<bit memory_port="mem_out[5]" value="1"/>
-			</bitstream>
-		</bitstream_block>
-		<bitstream_block name="mem_left_ipin_3" hierarchy_level="2">
-			<hierarchy>
-				<instance level="0" name="fpga_top"/>
-				<instance level="1" name="cby_2__2_"/>
-				<instance level="2" name="mem_left_ipin_3"/>
-			</hierarchy>
-			<input_nets>
-				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="a"/>
-				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="unmapped"/>
-			</input_nets>
-			<output_nets>
-				<path id="0" net_name="unmapped"/>
-			</output_nets>
-			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="0"/>
-				<bit memory_port="mem_out[2]" value="0"/>
-				<bit memory_port="mem_out[3]" value="0"/>
-				<bit memory_port="mem_out[4]" value="0"/>
-				<bit memory_port="mem_out[5]" value="1"/>
-			</bitstream>
-		</bitstream_block>
-		<bitstream_block name="mem_left_ipin_4" hierarchy_level="2">
-			<hierarchy>
-				<instance level="0" name="fpga_top"/>
-				<instance level="1" name="cby_2__2_"/>
-				<instance level="2" name="mem_left_ipin_4"/>
-			</hierarchy>
-			<input_nets>
-				<path id="0" net_name="a"/>
-				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="unmapped"/>
-			</input_nets>
-			<output_nets>
-				<path id="0" net_name="unmapped"/>
-			</output_nets>
-			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="0"/>
-				<bit memory_port="mem_out[2]" value="0"/>
-				<bit memory_port="mem_out[3]" value="0"/>
-				<bit memory_port="mem_out[4]" value="0"/>
-				<bit memory_port="mem_out[5]" value="1"/>
-			</bitstream>
-		</bitstream_block>
-		<bitstream_block name="mem_left_ipin_5" hierarchy_level="2">
-			<hierarchy>
-				<instance level="0" name="fpga_top"/>
-				<instance level="1" name="cby_2__2_"/>
-				<instance level="2" name="mem_left_ipin_5"/>
-			</hierarchy>
-			<input_nets>
-				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="unmapped"/>
-			</input_nets>
-			<output_nets>
-				<path id="0" net_name="unmapped"/>
-			</output_nets>
-			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="0"/>
-				<bit memory_port="mem_out[2]" value="0"/>
-				<bit memory_port="mem_out[3]" value="0"/>
-				<bit memory_port="mem_out[4]" value="0"/>
-				<bit memory_port="mem_out[5]" value="1"/>
-			</bitstream>
-		</bitstream_block>
-		<bitstream_block name="mem_left_ipin_6" hierarchy_level="2">
-			<hierarchy>
-				<instance level="0" name="fpga_top"/>
-				<instance level="1" name="cby_2__2_"/>
-				<instance level="2" name="mem_left_ipin_6"/>
-			</hierarchy>
-			<input_nets>
-				<path id="0" net_name="c"/>
-				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="unmapped"/>
-			</input_nets>
-			<output_nets>
-				<path id="0" net_name="unmapped"/>
-			</output_nets>
-			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="0"/>
-				<bit memory_port="mem_out[2]" value="0"/>
-				<bit memory_port="mem_out[3]" value="0"/>
-				<bit memory_port="mem_out[4]" value="0"/>
-				<bit memory_port="mem_out[5]" value="1"/>
-			</bitstream>
-		</bitstream_block>
-		<bitstream_block name="mem_left_ipin_7" hierarchy_level="2">
-			<hierarchy>
-				<instance level="0" name="fpga_top"/>
-				<instance level="1" name="cby_2__2_"/>
-				<instance level="2" name="mem_left_ipin_7"/>
-			</hierarchy>
-			<input_nets>
-				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="unmapped"/>
-				<path id="2" net_name="unmapped"/>
-				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="unmapped"/>
-			</input_nets>
-			<output_nets>
-				<path id="0" net_name="unmapped"/>
-			</output_nets>
-			<bitstream path_id="-1">
-				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="0"/>
-				<bit memory_port="mem_out[2]" value="0"/>
-				<bit memory_port="mem_out[3]" value="0"/>
-				<bit memory_port="mem_out[4]" value="0"/>
-				<bit memory_port="mem_out[5]" value="1"/>
-			</bitstream>
-		</bitstream_block>
 		<bitstream_block name="mem_right_ipin_0" hierarchy_level="2">
 			<hierarchy>
 				<instance level="0" name="fpga_top"/>
@@ -8783,23 +8783,23 @@
 				<instance level="2" name="mem_right_ipin_0"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="a"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 				<path id="2" net_name="unmapped"/>
 				<path id="3" net_name="unmapped"/>
-				<path id="4" net_name="unmapped"/>
-				<path id="5" net_name="unmapped"/>
+				<path id="4" net_name="b"/>
+				<path id="5" net_name="c"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="b"/>
 			</output_nets>
-			<bitstream path_id="-1">
+			<bitstream path_id="4">
 				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="0"/>
+				<bit memory_port="mem_out[1]" value="1"/>
 				<bit memory_port="mem_out[2]" value="0"/>
 				<bit memory_port="mem_out[3]" value="0"/>
-				<bit memory_port="mem_out[4]" value="0"/>
-				<bit memory_port="mem_out[5]" value="1"/>
+				<bit memory_port="mem_out[4]" value="1"/>
+				<bit memory_port="mem_out[5]" value="0"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_right_ipin_1" hierarchy_level="2">
@@ -8810,14 +8810,14 @@
 			</hierarchy>
 			<input_nets>
 				<path id="0" net_name="unmapped"/>
-				<path id="1" net_name="unmapped"/>
+				<path id="1" net_name="a"/>
 			</input_nets>
 			<output_nets>
-				<path id="0" net_name="unmapped"/>
+				<path id="0" net_name="a"/>
 			</output_nets>
-			<bitstream path_id="-1">
+			<bitstream path_id="1">
 				<bit memory_port="mem_out[0]" value="0"/>
-				<bit memory_port="mem_out[1]" value="0"/>
+				<bit memory_port="mem_out[1]" value="1"/>
 			</bitstream>
 		</bitstream_block>
 		<bitstream_block name="mem_right_ipin_2" hierarchy_level="2">
@@ -8827,7 +8827,7 @@
 				<instance level="2" name="mem_right_ipin_2"/>
 			</hierarchy>
 			<input_nets>
-				<path id="0" net_name="c"/>
+				<path id="0" net_name="unmapped"/>
 				<path id="1" net_name="unmapped"/>
 			</input_nets>
 			<output_nets>
diff --git a/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga
index 750a95b25..fd296d24e 100644
--- a/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/load_external_arch_bitstream_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --skip_sync_clustering_and_routing_results on
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --fix_clusters ${OPENFPGA_VPR_FIX_CLUSTERS} --skip_sync_clustering_and_routing_results on
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
diff --git a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
index 11cf542e3..4d1ef80e1 100644
--- a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
+++ b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
@@ -21,6 +21,8 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml
 openfpga_vpr_device_layout=2x2
+openfpga_vpr_route_chan_width=18
+openfpga_vpr_fix_clusters=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm.place
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml