Adding frac-lut-arch-explore_template
This commit is contained in:
Ganesh Gore
parent
669b1c7f3e
commit
b5e8434ca0
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = false
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:TASK_DIR}/vtr_benchmark_template_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
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vpr_route_chan_width=300
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[ARCHITECTURES]
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arch0=${PATH:TASK_DIR}/k6_N10_tileable.xml
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arch1=${PATH:TASK_DIR}/k6_frac_N10_tileable.xml
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[BENCHMARKS]
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bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v
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bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v
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bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v
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bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/sha.v
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[SYNTHESIS_PARAM]
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# Yosys script parameters
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bench_read_verilog_options_common = -nolatches
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bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
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# Benchmark top_module name
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bench1_top = memset
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bench2_top = diffeq_paj_convert
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bench3_top = diffeq_f_systemC
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bench4_top = sha1
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[SCRIPT_PARAM_]
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#
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@ -0,0 +1,302 @@
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<?xml version="1.0" ?>
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<architecture>
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<models>
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<model name="adder">
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<input_ports>
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<port name="a" combinational_sink_ports="sumout cout"/>
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<port name="b" combinational_sink_ports="sumout cout"/>
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<port name="cin" combinational_sink_ports="sumout cout"/>
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</input_ports>
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<output_ports>
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<port name="cout"/>
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<port name="sumout"/>
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</output_ports>
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</model>
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<model name="io">
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<input_ports>
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<port name="outpad"/>
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</input_ports>
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<output_ports>
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<port name="inpad"/>
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</output_ports>
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</model>
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<model name="frac_lut6">
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<input_ports>
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<port name="in"/>
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</input_ports>
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<output_ports>
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<port name="lut4_out"/>
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<port name="lut5_out"/>
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<port name="lut6_out"/>
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</output_ports>
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</model>
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</models>
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<tiles>
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<tile name="io" area="0">
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<sub_tile name="io" capacity="8">
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<equivalent_sites>
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<site pb_type="io"/>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="custom">
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<loc side="left">io.outpad io.inpad</loc>
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<loc side="top">io.outpad io.inpad</loc>
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<loc side="right">io.outpad io.inpad</loc>
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<loc side="bottom">io.outpad io.inpad</loc>
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</pinlocations>
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</sub_tile>
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</tile>
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<tile name="clb" area="53894">
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<sub_tile name="clb">
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<equivalent_sites>
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<site pb_type="clb"/>
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</equivalent_sites>
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<input name="I" num_pins="40" equivalent="full"/>
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<input name="cin" num_pins="1"/>
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<output name="O" num_pins="20" equivalent="none"/>
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<output name="cout" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
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<fc_override port_name="cin" fc_type="frac" fc_val="0"/>
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<fc_override port_name="cout" fc_type="frac" fc_val="0" />
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</fc>
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<pinlocations pattern="custom">
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<loc side="left">clb.clk</loc>
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<loc side="top">clb.cin</loc>
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<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
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<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
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</pinlocations>
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</sub_tile>
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</tile>
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</tiles>
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
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<layout tileable="true" through_channel="false">
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<auto_layout aspect_ratio="1.0">
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<fill type="clb" priority="10"/>
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<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
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</auto_layout>
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<fixed_layout name="3x2" width="5" height="4">
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<fill type="clb" priority="10"/>
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<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
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</fixed_layout>
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</layout>
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<device>
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<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
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<area grid_logic_tile_area="0"/>
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<chan_width_distr>
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<x distr="uniform" peak="1.000000"/>
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<switch_block type="wilton" fs="3"/>
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<connection_block input_switch_name="ipin_cblock"/>
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</device>
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<switchlist>
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<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
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</switchlist>
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<segmentlist>
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<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
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<mux name="0"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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</segment>
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</segmentlist>
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<complexblocklist>
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<pb_type name="io">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<mode name="physical" disable_packing="true">
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<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="iopad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
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</direct>
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<direct name="inpad" input="iopad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="inpad">
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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</direct>
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</interconnect>
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</mode>
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<power method="ignore"/>
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</pb_type>
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<pb_type name="clb">
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<input name="I" num_pins="40" equivalent="full"/>
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<input name="cin" num_pins="1"/>
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<output name="O" num_pins="20" equivalent="none"/>
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<output name="cout" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="fle" num_pb="10">
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<input name="in" num_pins="6"/>
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<input name="cin" num_pins="1"/>
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<output name="out" num_pins="2"/>
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<output name="cout" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- Physical mode definition begin (physical implementation of the fle) -->
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<mode name="physical" disable_packing="true">
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<pb_type name="fabric" num_pb="1">
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<input name="in" num_pins="6"/>
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<input name="cin" num_pins="1"/>
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<output name="out" num_pins="2"/>
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<output name="cout" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="frac_logic" num_pb="1">
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<input name="in" num_pins="6"/>
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<output name="lut4_out" num_pins="4"/>
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<output name="out" num_pins="2"/>
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<!-- Define LUT -->
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<pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
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<input name="in" num_pins="6"/>
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<output name="lut4_out" num_pins="4"/>
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<output name="lut5_out" num_pins="2"/>
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<output name="lut6_out" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
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<direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
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<direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
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<mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
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</interconnect>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<!-- Define adders -->
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<pb_type name="adder" blif_model=".subckt adder" num_pb="2">
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<input name="a" num_pins="1"/>
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<input name="b" num_pins="1"/>
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<input name="cin" num_pins="1"/>
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<output name="cout" num_pins="1"/>
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<output name="sumout" num_pins="1"/>
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<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
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<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
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<delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
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<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
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<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
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<delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
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<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
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<direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
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<direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
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<direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
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<direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
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<direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
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<direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
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<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
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<complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
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<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
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<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
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</mux>
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<mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
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<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
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</mux>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fle.in" output="fabric.in"/>
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<direct name="direct2" input="fle.cin" output="fabric.cin"/>
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<direct name="direct3" input="fabric.out" output="fle.out"/>
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<direct name="direct4" input="fabric.cout" output="fle.cout"/>
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<direct name="direct5" input="fle.clk" output="fabric.clk"/>
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</interconnect>
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</mode>
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<!-- Physical mode definition end (physical implementation of the fle) -->
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<!-- n2_lut5 -->
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<mode name="n1_lut6">
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<pb_type name="ble6" num_pb="1">
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<input name="in" num_pins="6"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
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<input name="in" num_pins="6" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
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261e-12
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261e-12
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261e-12
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261e-12
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261e-12
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261e-12
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</delay_matrix>
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</pb_type>
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
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<direct name="direct2" input="lut6.out" output="ff.D">
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<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
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</direct>
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<direct name="direct3" input="ble6.clk" output="ff.clk"/>
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<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
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<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
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<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
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</mux>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
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<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
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<direct name="direct3" input="fle.clk" output="ble6.clk"/>
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</interconnect>
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</mode>
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<!-- n1_lut6 -->
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</pb_type>
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<interconnect>
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<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
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<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
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<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
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</complete>
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<complete name="clks" input="clb.clk" output="fle[9:0].clk">
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</complete>
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<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
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<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
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</interconnect>
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</pb_type>
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</complexblocklist>
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</architecture>
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@ -0,0 +1,355 @@
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<?xml version="1.0" ?>
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<architecture>
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<models>
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<model name="adder">
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<input_ports>
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<port name="a" combinational_sink_ports="sumout cout"/>
|
||||
<port name="b" combinational_sink_ports="sumout cout"/>
|
||||
<port name="cin" combinational_sink_ports="sumout cout"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="cout"/>
|
||||
<port name="sumout"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<model name="io">
|
||||
<input_ports>
|
||||
<port name="outpad"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="inpad"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<model name="frac_lut6">
|
||||
<input_ports>
|
||||
<port name="in"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="lut4_out"/>
|
||||
<port name="lut5_out"/>
|
||||
<port name="lut6_out"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
</models>
|
||||
<tiles>
|
||||
<tile name="io" area="0">
|
||||
<sub_tile name="io" capacity="8">
|
||||
<equivalent_sites>
|
||||
<site pb_type="io"/>
|
||||
</equivalent_sites>
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">io.outpad io.inpad</loc>
|
||||
<loc side="top">io.outpad io.inpad</loc>
|
||||
<loc side="right">io.outpad io.inpad</loc>
|
||||
<loc side="bottom">io.outpad io.inpad</loc>
|
||||
</pinlocations>
|
||||
</sub_tile>
|
||||
</tile>
|
||||
<tile name="clb" area="53894">
|
||||
<sub_tile name="clb">
|
||||
<equivalent_sites>
|
||||
<site pb_type="clb"/>
|
||||
</equivalent_sites>
|
||||
<input name="I" num_pins="40" equivalent="full"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="O" num_pins="20" equivalent="none"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
|
||||
<fc_override port_name="cin" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="cout" fc_type="frac" fc_val="0" />
|
||||
</fc>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">clb.clk</loc>
|
||||
<loc side="top">clb.cin</loc>
|
||||
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
|
||||
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
|
||||
</pinlocations>
|
||||
</sub_tile>
|
||||
</tile>
|
||||
</tiles>
|
||||
<!-- ODIN II specific config ends -->
|
||||
<!-- Physical descriptions begin -->
|
||||
<layout tileable="true" through_channel="false">
|
||||
<auto_layout aspect_ratio="1.0">
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<fill type="clb" priority="10"/>
|
||||
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
|
||||
</auto_layout>
|
||||
<fixed_layout name="3x2" width="5" height="4">
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<fill type="clb" priority="10"/>
|
||||
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
|
||||
</fixed_layout>
|
||||
</layout>
|
||||
<device>
|
||||
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
|
||||
<area grid_logic_tile_area="0"/>
|
||||
<chan_width_distr>
|
||||
<x distr="uniform" peak="1.000000"/>
|
||||
<y distr="uniform" peak="1.000000"/>
|
||||
</chan_width_distr>
|
||||
<switch_block type="wilton" fs="3"/>
|
||||
<connection_block input_switch_name="ipin_cblock"/>
|
||||
</device>
|
||||
<switchlist>
|
||||
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
|
||||
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
|
||||
</switchlist>
|
||||
<segmentlist>
|
||||
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
|
||||
<mux name="0"/>
|
||||
<sb type="pattern">1 1 1 1 1</sb>
|
||||
<cb type="pattern">1 1 1 1</cb>
|
||||
</segment>
|
||||
</segmentlist>
|
||||
<complexblocklist>
|
||||
<pb_type name="io">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<mode name="physical" disable_packing="true">
|
||||
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="iopad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
|
||||
</direct>
|
||||
<direct name="inpad" input="iopad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="inpad">
|
||||
<pb_type name="inpad" blif_model=".input" num_pb="1">
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="inpad" input="inpad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="outpad">
|
||||
<pb_type name="outpad" blif_model=".output" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="outpad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<power method="ignore"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb">
|
||||
<input name="I" num_pins="40" equivalent="full"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="O" num_pins="20" equivalent="none"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="fle" num_pb="10">
|
||||
<input name="in" num_pins="6"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Physical mode definition begin (physical implementation of the fle) -->
|
||||
<mode name="physical" disable_packing="true">
|
||||
<pb_type name="fabric" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="frac_logic" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
<output name="lut4_out" num_pins="4"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<!-- Define LUT -->
|
||||
<pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
<output name="lut4_out" num_pins="4"/>
|
||||
<output name="lut5_out" num_pins="2"/>
|
||||
<output name="lut6_out" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
|
||||
<direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
|
||||
<direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
|
||||
<mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<!-- Define flip-flop -->
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<!-- Define adders -->
|
||||
<pb_type name="adder" blif_model=".subckt adder" num_pb="2">
|
||||
<input name="a" num_pins="1"/>
|
||||
<input name="b" num_pins="1"/>
|
||||
<input name="cin" num_pins="1"/>
|
||||
<output name="cout" num_pins="1"/>
|
||||
<output name="sumout" num_pins="1"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
|
||||
<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
|
||||
<delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
|
||||
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
|
||||
<direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
|
||||
<direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
|
||||
<direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
|
||||
<direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
|
||||
<direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
|
||||
<direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
|
||||
<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
|
||||
<complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
|
||||
<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
|
||||
</mux>
|
||||
<mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="fabric.in"/>
|
||||
<direct name="direct2" input="fle.cin" output="fabric.cin"/>
|
||||
<direct name="direct3" input="fabric.out" output="fle.out"/>
|
||||
<direct name="direct4" input="fabric.cout" output="fle.cout"/>
|
||||
<direct name="direct5" input="fle.clk" output="fabric.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Physical mode definition end (physical implementation of the fle) -->
|
||||
<!-- BEGIN fle mode of dual lut5 -->
|
||||
<mode name="n2_lut5">
|
||||
<pb_type name="ble5" num_pb="2">
|
||||
<input name="in" num_pins="5"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Regular LUT mode -->
|
||||
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="5" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||
we instead take the average of these numbers to get more stable results
|
||||
82e-12
|
||||
173e-12
|
||||
261e-12
|
||||
263e-12
|
||||
398e-12
|
||||
-->
|
||||
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
|
||||
235e-12
|
||||
235e-12
|
||||
235e-12
|
||||
235e-12
|
||||
235e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble5.in" output="lut5.in"/>
|
||||
<direct name="direct2" input="lut5.out" output="ff.D">
|
||||
<pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble5.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
|
||||
<delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
|
||||
<direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
|
||||
<complete name="direct3" input="fle.clk" output="ble5.clk"/>
|
||||
<direct name="direct4" input="ble5.out" output="fle.out"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- n2_lut5 -->
|
||||
<mode name="n1_lut6">
|
||||
<pb_type name="ble6" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="6" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
|
||||
<direct name="direct2" input="lut6.out" output="ff.D">
|
||||
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
|
||||
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
|
||||
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- n1_lut6 -->
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
|
||||
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
|
||||
<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
|
||||
</complete>
|
||||
|
||||
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
|
||||
</complete>
|
||||
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
|
||||
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
|
||||
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
</complexblocklist>
|
||||
</architecture>
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
# Execute VPR for architecture exploration
|
||||
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \
|
||||
--route_chan_width ${VPR_ROUTE_CHAN_WIDTH} \
|
||||
--constant_net_method route
|
||||
|
||||
exit
|
||||
Loading…
Reference in New Issue