diff --git a/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/config/task.conf b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/config/task.conf
new file mode 100644
index 000000000..b7a70963c
--- /dev/null
+++ b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/config/task.conf
@@ -0,0 +1,46 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:TASK_DIR}/vtr_benchmark_template_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+vpr_route_chan_width=300
+
+[ARCHITECTURES]
+arch0=${PATH:TASK_DIR}/k6_N10_tileable.xml
+arch1=${PATH:TASK_DIR}/k6_frac_N10_tileable.xml
+
+[BENCHMARKS]
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v
+bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v
+bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/sha.v
+
+[SYNTHESIS_PARAM]
+# Yosys script parameters
+bench_read_verilog_options_common = -nolatches
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
+
+# Benchmark top_module name
+bench1_top = memset
+bench2_top = diffeq_paj_convert
+bench3_top = diffeq_f_systemC
+bench4_top = sha1
+
+[SCRIPT_PARAM_]
+#
\ No newline at end of file
diff --git a/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_N10_tileable.xml b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_N10_tileable.xml
new file mode 100644
index 000000000..4510490d4
--- /dev/null
+++ b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_N10_tileable.xml
@@ -0,0 +1,302 @@
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+ io.outpad io.inpad
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+ clb.clk
+ clb.cin
+ clb.O[9:0] clb.I[19:0]
+ clb.cout clb.O[19:10] clb.I[39:20]
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diff --git a/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_frac_N10_tileable.xml b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_frac_N10_tileable.xml
new file mode 100644
index 000000000..a9ef774a9
--- /dev/null
+++ b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/k6_frac_N10_tileable.xml
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+ clb.cout clb.O[19:10] clb.I[39:20]
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diff --git a/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/vtr_benchmark_template_script.openfpga b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/vtr_benchmark_template_script.openfpga
new file mode 100644
index 000000000..ebe778df6
--- /dev/null
+++ b/openfpga_flow/tasks/template_tasks/frac-lut-arch-explore_template/vtr_benchmark_template_script.openfpga
@@ -0,0 +1,7 @@
+# Execute VPR for architecture exploration
+
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \
+ --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} \
+ --constant_net_method route
+
+exit
\ No newline at end of file