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Test image resizing

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Baudouin Chauviere 2018-10-09 15:07:23 -06:00
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examples/Examples_README.md
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@ -7,7 +7,7 @@ The .xml is currently on <layout auto="1.0"/> which means that the size depends
almost empty, only 1 CLB will be generated. almost empty, only 1 CLB will be generated.
![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_1.png "Example_1_FPGA") ![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_1.png "Example_1_FPGA")
<img src="https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_1.png" alt="Example_1_FPGA" width="80%">
Schematic of the FPGA generated during example_1. Schematic of the FPGA generated during example_1.
The CLB integrates a 4-inputs LUT, a FF and a MUX. The CLB integrates a 4-inputs LUT, a FF and a MUX.
@ -45,14 +45,14 @@ Everything won't be explained in detail but few important structures (some commo
</architecture> </architecture>
``` ```
---
## Example_2 ## Example_2
Example_2's goal is to introduce the slices, the interconnections which can be generated from it and the manual mode of the layout. Example_2's goal is to introduce the slices, the interconnections which can be generated from it and the manual mode of the layout.
In this case, we generate a 3x3 FPGA with 4 slices. The LUTs are 6-inputs ones similarly to the ones used in the industry. In this case, we generate a 3x3 FPGA with 4 slices. The LUTs are 6-inputs ones similarly to the ones used in the industry.
There is a feedbeck-loop from the output of the slices to the input MUXs There is a feedback-loop from the output of the slices to the input MUXs
![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_the_CLB.png "Example_2_CLB") ![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_the_CLB.png "Example_2_CLB"){:height="80%" width="80%"}
Schematic showing the CLB generated in this example. Schematic showing the CLB generated in this example.
@ -70,6 +70,8 @@ Schematic showing the CLB generated in this example.
</complete> </complete>
``` ```
![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_3x3.png "Example_3_FPGA"){:height="80%" width="80%"}