diff --git a/examples/Examples_README.md b/examples/Examples_README.md
index 1c11126bb..6c3283caf 100644
--- a/examples/Examples_README.md
+++ b/examples/Examples_README.md
@@ -7,7 +7,7 @@ The .xml is currently on <layout auto="1.0"/> which means that the size depends
 almost empty, only 1 CLB will be generated. 
 
 ![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_1.png "Example_1_FPGA")
-
+<img src="https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_1.png" alt="Example_1_FPGA" width="80%">
 Schematic of the FPGA generated during example_1.
 The CLB integrates a 4-inputs LUT, a FF and a MUX. 
 
@@ -45,14 +45,14 @@ Everything won't be explained in detail but few important structures (some commo
 </architecture>
 ```
 
-
+---
 ## Example_2
 
 Example_2's goal is to introduce the slices, the interconnections which can be generated from it and the manual mode of the layout.
 In this case, we generate a 3x3 FPGA with 4 slices. The LUTs are 6-inputs ones similarly to the ones used in the industry.
-There is a feedbeck-loop from the output of the slices to the input MUXs
+There is a feedback-loop from the output of the slices to the input MUXs
 
-![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_the_CLB.png "Example_2_CLB")
+![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_the_CLB.png "Example_2_CLB"){:height="80%" width="80%"}
 
 Schematic showing the CLB generated in this example.
 
@@ -69,6 +69,8 @@ Schematic showing the CLB generated in this example.
 	<delay_constant max="53.44e-12" in_port="fle[3:0].out" out_port="fle[3:0].in" />
 </complete>
 ```
+
+![alt text](https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_3x3.png "Example_3_FPGA"){:height="80%" width="80%"}