Test image resizing
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@ -7,7 +7,7 @@ The .xml is currently on <layout auto="1.0"/> which means that the size depends
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almost empty, only 1 CLB will be generated.
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
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<img src="https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_1.png" alt="Example_1_FPGA" width="80%">
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Schematic of the FPGA generated during example_1.
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The CLB integrates a 4-inputs LUT, a FF and a MUX.
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@ -45,14 +45,14 @@ Everything won't be explained in detail but few important structures (some commo
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</architecture>
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```
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---
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## Example_2
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Example_2's goal is to introduce the slices, the interconnections which can be generated from it and the manual mode of the layout.
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In this case, we generate a 3x3 FPGA with 4 slices. The LUTs are 6-inputs ones similarly to the ones used in the industry.
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There is a feedbeck-loop from the output of the slices to the input MUXs
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There is a feedback-loop from the output of the slices to the input MUXs
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
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{:height="80%" width="80%"}
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Schematic showing the CLB generated in this example.
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@ -69,6 +69,8 @@ Schematic showing the CLB generated in this example.
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<delay_constant max="53.44e-12" in_port="fle[3:0].out" out_port="fle[3:0].in" />
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</complete>
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```
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{:height="80%" width="80%"}
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