riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] code format

This commit is contained in:
tangxifan 2023-11-03 13:50:04 -07:00
parent 21813eb59f
commit b2e1eb30c7
1 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -1627,12 +1627,14 @@ static void print_verilog_full_testbench_configuration_chain_bitstream(
config_protocol.prog_clock_pin_ccff_head_indices( config_protocol.prog_clock_pin_ccff_head_indices(
config_protocol.prog_clock_pins()[iclk]); config_protocol.prog_clock_pins()[iclk]);
size_t curr_regional_bitstream_max_size = size_t curr_regional_bitstream_max_size =
find_fabric_regional_bitstream_max_size(fabric_bitstream, curr_clk_ctrl_regions); find_fabric_regional_bitstream_max_size(fabric_bitstream,
curr_clk_ctrl_regions);
size_t curr_num_bits_to_skip = 0; size_t curr_num_bits_to_skip = 0;
if (true == fast_configuration) { if (true == fast_configuration) {
curr_num_bits_to_skip = curr_num_bits_to_skip =
find_configuration_chain_fabric_bitstream_size_to_be_skipped( find_configuration_chain_fabric_bitstream_size_to_be_skipped(
fabric_bitstream, bitstream_manager, bit_value_to_skip, curr_clk_ctrl_regions); fabric_bitstream, bitstream_manager, bit_value_to_skip,
curr_clk_ctrl_regions);
} }
/* TODO: Try to apply different length as the bitstream size for ccffs are /* TODO: Try to apply different length as the bitstream size for ccffs are
* different driven by differnt clocks! Tried but no luck yet. */ * different driven by differnt clocks! Tried but no luck yet. */
@ -1917,11 +1919,12 @@ static void print_verilog_full_testbench_configuration_chain_bitstream(
VTR_ASSERT(num_prog_clocks > 1); VTR_ASSERT(num_prog_clocks > 1);
for (size_t iclk = 0; iclk < num_prog_clocks; ++iclk) { for (size_t iclk = 0; iclk < num_prog_clocks; ++iclk) {
BasicPort curr_prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME) + BasicPort curr_prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME) +
std::string(TOP_TB_CLOCK_REG_POSTFIX), std::string(TOP_TB_CLOCK_REG_POSTFIX),
iclk, iclk); iclk, iclk);
fp << "always"; fp << "always";
fp << " @(negedge " fp << " @(negedge "
<< generate_verilog_port(VERILOG_PORT_CONKT, curr_prog_clock_port) << ")"; << generate_verilog_port(VERILOG_PORT_CONKT, curr_prog_clock_port)
<< ")";
fp << " begin"; fp << " begin";
fp << std::endl; fp << std::endl;