diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index f10a065a0..d62b3f143 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -1627,12 +1627,14 @@ static void print_verilog_full_testbench_configuration_chain_bitstream(
         config_protocol.prog_clock_pin_ccff_head_indices(
           config_protocol.prog_clock_pins()[iclk]);
       size_t curr_regional_bitstream_max_size =
-        find_fabric_regional_bitstream_max_size(fabric_bitstream, curr_clk_ctrl_regions);
+        find_fabric_regional_bitstream_max_size(fabric_bitstream,
+                                                curr_clk_ctrl_regions);
       size_t curr_num_bits_to_skip = 0;
       if (true == fast_configuration) {
-        curr_num_bits_to_skip = 
+        curr_num_bits_to_skip =
           find_configuration_chain_fabric_bitstream_size_to_be_skipped(
-            fabric_bitstream, bitstream_manager, bit_value_to_skip, curr_clk_ctrl_regions);
+            fabric_bitstream, bitstream_manager, bit_value_to_skip,
+            curr_clk_ctrl_regions);
       }
       /* TODO: Try to apply different length as the bitstream size for ccffs are
        * different driven by differnt clocks! Tried but no luck yet. */
@@ -1917,11 +1919,12 @@ static void print_verilog_full_testbench_configuration_chain_bitstream(
     VTR_ASSERT(num_prog_clocks > 1);
     for (size_t iclk = 0; iclk < num_prog_clocks; ++iclk) {
       BasicPort curr_prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME) +
-                                  std::string(TOP_TB_CLOCK_REG_POSTFIX),
-                                iclk, iclk);
+                                       std::string(TOP_TB_CLOCK_REG_POSTFIX),
+                                     iclk, iclk);
       fp << "always";
       fp << " @(negedge "
-         << generate_verilog_port(VERILOG_PORT_CONKT, curr_prog_clock_port) << ")";
+         << generate_verilog_port(VERILOG_PORT_CONKT, curr_prog_clock_port)
+         << ")";
       fp << " begin";
       fp << std::endl;