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[Tool] Patch bugs in the full testbench writing using external bitstream file for frame-based configuration protocol

This commit is contained in:
tangxifan 2021-06-07 13:53:32 -06:00
parent d644b8f22d
commit af298de121
2 changed files with 6 additions and 2 deletions
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3
openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp
View File

@ -240,8 +240,7 @@ int write_frame_based_fabric_bitstream_to_text_file(std::fstream& fp,
/* Output information about how to intepret the bitstream */
fp << "// Bitstream length: " << fabric_bits_by_addr.size() - num_bits_to_skip << std::endl;
fp << "// Bitstream address size (LSB -> MSB): " << addr_size << std::endl;
fp << "// Bitstream data input size (LSB -> MSB): " << din_size << std::endl;
fp << "// Bitstream width (LSB -> MSB): <address " << addr_size << " bits><data input " << din_size << " bits>" << std::endl;
for (const auto& addr_din_pair : fabric_bits_by_addr) {
/* When fast configuration is enabled,

5
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -2191,6 +2191,11 @@ void print_verilog_full_testbench_frame_decoder_bitstream(std::fstream& fp,
fp << ";";
fp << std::endl;
fp << "\t";
fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << " <= 0";
fp << ";";
fp << std::endl;
fp << "end";
fp << std::endl;