From af298de12143acfbc9cbd6e85664f7ef56183e15 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 7 Jun 2021 13:53:32 -0600
Subject: [PATCH] [Tool] Patch bugs in the full testbench writing using
 external bitstream file for frame-based configuration protocol

---
 openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp | 3 +--
 openfpga/src/fpga_verilog/verilog_top_testbench.cpp         | 5 +++++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp
index 0e8a435e7..57d8d92e1 100644
--- a/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp
@@ -240,8 +240,7 @@ int write_frame_based_fabric_bitstream_to_text_file(std::fstream& fp,
 
   /* Output information about how to intepret the bitstream */
   fp << "// Bitstream length: " << fabric_bits_by_addr.size() - num_bits_to_skip << std::endl;
-  fp << "// Bitstream address size (LSB -> MSB): " << addr_size << std::endl;
-  fp << "// Bitstream data input size (LSB -> MSB): " << din_size << std::endl;
+  fp << "// Bitstream width (LSB -> MSB): <address " << addr_size << " bits><data input " << din_size << " bits>" << std::endl;
 
   for (const auto& addr_din_pair : fabric_bits_by_addr) {
     /* When fast configuration is enabled,
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 951611c39..20f3a5bcb 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -2191,6 +2191,11 @@ void print_verilog_full_testbench_frame_decoder_bitstream(std::fstream& fp,
   fp << ";";
   fp << std::endl;
 
+  fp << "\t";
+  fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << " <= 0";
+  fp << ";";
+  fp << std::endl;
+
   fp << "end";
   fp << std::endl;