[doc] update fig

2024-09-21 13:35:42 -07:00 · 2024-09-21 13:35:42 -07:00 · af09120a52
parent 26cda624d3
commit af09120a52
2 changed files with 4 additions and 1 deletions
--- a/docs/source/manual/file_formats/clock_network.rst
+++ b/docs/source/manual/file_formats/clock_network.rst
@ -224,7 +224,10 @@ For example,
    <spine>
  </clock_network>
-where the clock routing can be driven at (x=1,y=1) by the output pins ``O[0:3]`` of tile ``clb`` in a VPR architecture description file:
+
 where clock spine ``spine0`` will be driven by other programmable blocks at (1, 1), as highlighted in purple in the :numref:`fig_prog_clock_network_example_2x2_perimeter_cb`
 To be specific, the clock routing can be driven at (x=1,y=1) by the output pins ``O[0:3]`` of tile ``clb`` in a VPR architecture description file:
 .. code-block:: xml
--- a/docs/source/manual/file_formats/figures/prog_clk_network_example_2x2_perimeter_cb.png
+++ b/docs/source/manual/file_formats/figures/prog_clk_network_example_2x2_perimeter_cb.png