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[core] format

This commit is contained in:
tangxifan 2024-05-31 19:44:40 -07:00
parent 93ebbef851
commit ad8ad25250
1 changed files with 20 additions and 16 deletions
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36
openfpga/src/utils/physical_pb_utils.cpp
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@ -190,14 +190,16 @@ static void synchronize_primitive_physical_pb_atom_nets(
pb_graph_node->input_pins[iport][ipin].to_string().c_str()); pb_graph_node->input_pins[iport][ipin].to_string().c_str());
t_model_ports* model_port = t_model_ports* model_port =
pb_graph_node->input_pins[iport][ipin].port->model_port; pb_graph_node->input_pins[iport][ipin].port->model_port;
/* Special for LUTs, the model port is hidden under 1 level */ /* Special for LUTs, the model port is hidden under 1 level
// Do NOT do this. Net mapping on LUT inputs may be swapped during rerouting * Do NOT do this. Net mapping on LUT inputs may be swapped during
//if (LUT_CLASS == pb_graph_node->pb_type->class_type) { * rerouting
// VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2); * if (LUT_CLASS == pb_graph_node->pb_type->class_type) {
// model_port = pb_graph_node->child_pb_graph_nodes[1][0][0] * VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2);
// .input_pins[iport][ipin] * model_port = pb_graph_node->child_pb_graph_nodes[1][0][0]
// .port->model_port; * .input_pins[iport][ipin]
//} * .port->model_port;
* }
*/
/* It seems that LUT port are no longer built with an internal model */ /* It seems that LUT port are no longer built with an internal model */
if (nullptr == model_port) { if (nullptr == model_port) {
VTR_LOGV(verbose, "Skip due to empty model port\n"); VTR_LOGV(verbose, "Skip due to empty model port\n");
@ -228,14 +230,16 @@ static void synchronize_primitive_physical_pb_atom_nets(
pb_graph_node->output_pins[iport][ipin].to_string().c_str()); pb_graph_node->output_pins[iport][ipin].to_string().c_str());
t_model_ports* model_port = t_model_ports* model_port =
pb_graph_node->output_pins[iport][ipin].port->model_port; pb_graph_node->output_pins[iport][ipin].port->model_port;
/* Special for LUTs, the model port is hidden under 1 level */ /* Special for LUTs, the model port is hidden under 1 level
// Do NOT do this. Net mapping on LUT inputs may be swapped during rerouting * Do NOT do this. Net mapping on LUT inputs may be swapped during
//if (LUT_CLASS == pb_graph_node->pb_type->class_type) { * rerouting
// VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2); * if (LUT_CLASS == pb_graph_node->pb_type->class_type) {
// model_port = pb_graph_node->child_pb_graph_nodes[1][0][0] * VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2);
// .output_pins[iport][ipin] * model_port = pb_graph_node->child_pb_graph_nodes[1][0][0]
// .port->model_port; * .output_pins[iport][ipin]
//} * .port->model_port;
* }
*/
if (nullptr == model_port) { if (nullptr == model_port) {
VTR_LOGV(verbose, "Skip due to empty model port\n"); VTR_LOGV(verbose, "Skip due to empty model port\n");
continue; continue;