From ad8ad25250e8a703948236ed64ac9ea4e954635c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 31 May 2024 19:44:40 -0700 Subject: [PATCH] [core] format --- openfpga/src/utils/physical_pb_utils.cpp | 36 +++++++++++++----------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/openfpga/src/utils/physical_pb_utils.cpp b/openfpga/src/utils/physical_pb_utils.cpp index 29a2164d2..ddb8c954f 100644 --- a/openfpga/src/utils/physical_pb_utils.cpp +++ b/openfpga/src/utils/physical_pb_utils.cpp @@ -190,14 +190,16 @@ static void synchronize_primitive_physical_pb_atom_nets( pb_graph_node->input_pins[iport][ipin].to_string().c_str()); t_model_ports* model_port = pb_graph_node->input_pins[iport][ipin].port->model_port; - /* Special for LUTs, the model port is hidden under 1 level */ - // Do NOT do this. Net mapping on LUT inputs may be swapped during rerouting - //if (LUT_CLASS == pb_graph_node->pb_type->class_type) { - // VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2); - // model_port = pb_graph_node->child_pb_graph_nodes[1][0][0] - // .input_pins[iport][ipin] - // .port->model_port; - //} + /* Special for LUTs, the model port is hidden under 1 level + * Do NOT do this. Net mapping on LUT inputs may be swapped during + * rerouting + * if (LUT_CLASS == pb_graph_node->pb_type->class_type) { + * VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2); + * model_port = pb_graph_node->child_pb_graph_nodes[1][0][0] + * .input_pins[iport][ipin] + * .port->model_port; + * } + */ /* It seems that LUT port are no longer built with an internal model */ if (nullptr == model_port) { VTR_LOGV(verbose, "Skip due to empty model port\n"); @@ -228,14 +230,16 @@ static void synchronize_primitive_physical_pb_atom_nets( pb_graph_node->output_pins[iport][ipin].to_string().c_str()); t_model_ports* model_port = pb_graph_node->output_pins[iport][ipin].port->model_port; - /* Special for LUTs, the model port is hidden under 1 level */ - // Do NOT do this. Net mapping on LUT inputs may be swapped during rerouting - //if (LUT_CLASS == pb_graph_node->pb_type->class_type) { - // VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2); - // model_port = pb_graph_node->child_pb_graph_nodes[1][0][0] - // .output_pins[iport][ipin] - // .port->model_port; - //} + /* Special for LUTs, the model port is hidden under 1 level + * Do NOT do this. Net mapping on LUT inputs may be swapped during + * rerouting + * if (LUT_CLASS == pb_graph_node->pb_type->class_type) { + * VTR_ASSERT(pb_graph_node->pb_type->num_modes == 2); + * model_port = pb_graph_node->child_pb_graph_nodes[1][0][0] + * .output_pins[iport][ipin] + * .port->model_port; + * } + */ if (nullptr == model_port) { VTR_LOGV(verbose, "Skip due to empty model port\n"); continue;