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[Arch] Patched superLUT architecture example when trying adder8 synthesis script

This commit is contained in:
tangxifan 2021-02-23 19:00:27 -07:00
parent 53df7f69e7
commit ad25944e59
1 changed files with 22 additions and 23 deletions
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45
openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -125,21 +125,21 @@
<equivalent_sites> <equivalent_sites>
<site pb_type="clb"/> <site pb_type="clb"/>
</equivalent_sites> </equivalent_sites>
<input name="I0" num_pins="2" equivalent="full"/> <input name="I0" num_pins="2" equivalent="none"/>
<input name="I0i" num_pins="2" equivalent="none"/> <input name="I0i" num_pins="2" equivalent="none"/>
<input name="I1" num_pins="2" equivalent="full"/> <input name="I1" num_pins="2" equivalent="none"/>
<input name="I1i" num_pins="2" equivalent="none"/> <input name="I1i" num_pins="2" equivalent="none"/>
<input name="I2" num_pins="2" equivalent="full"/> <input name="I2" num_pins="2" equivalent="none"/>
<input name="I2i" num_pins="2" equivalent="none"/> <input name="I2i" num_pins="2" equivalent="none"/>
<input name="I3" num_pins="2" equivalent="full"/> <input name="I3" num_pins="2" equivalent="none"/>
<input name="I3i" num_pins="2" equivalent="none"/> <input name="I3i" num_pins="2" equivalent="none"/>
<input name="I4" num_pins="2" equivalent="full"/> <input name="I4" num_pins="2" equivalent="none"/>
<input name="I4i" num_pins="2" equivalent="none"/> <input name="I4i" num_pins="2" equivalent="none"/>
<input name="I5" num_pins="2" equivalent="full"/> <input name="I5" num_pins="2" equivalent="none"/>
<input name="I5i" num_pins="2" equivalent="none"/> <input name="I5i" num_pins="2" equivalent="none"/>
<input name="I6" num_pins="2" equivalent="full"/> <input name="I6" num_pins="2" equivalent="none"/>
<input name="I6i" num_pins="2" equivalent="none"/> <input name="I6i" num_pins="2" equivalent="none"/>
<input name="I7" num_pins="2" equivalent="full"/> <input name="I7" num_pins="2" equivalent="none"/>
<input name="I7i" num_pins="2" equivalent="none"/> <input name="I7i" num_pins="2" equivalent="none"/>
<input name="reg_in" num_pins="1"/> <input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/> <input name="sc_in" num_pins="1"/>
@ -333,27 +333,27 @@
</pb_type> </pb_type>
<!-- Define I/O pads ends --> <!-- Define I/O pads ends -->
<!-- Define general purpose logic block (CLB) begin --> <!-- Define general purpose logic block (CLB) begin -->
<!-- -Due to the absence of local routing, <!-- Due to that LUT bitstream may be overwritten by .eblif files
the 4 inputs of fracturable LUT4 are no longer equivalent, Pin equivalence of CLB inputs are all disabled.
because the 4th input can not be switched when the dual-LUT3 modes are used. This is because the hard coded bitstream in .eblif cannot be
So pin equivalence should be applied to the first 3 inputs only adapted to the net swapping from VPR's routing optimization
--> -->
<pb_type name="clb"> <pb_type name="clb">
<input name="I0" num_pins="2" equivalent="full"/> <input name="I0" num_pins="2" equivalent="none"/>
<input name="I0i" num_pins="2" equivalent="none"/> <input name="I0i" num_pins="2" equivalent="none"/>
<input name="I1" num_pins="2" equivalent="full"/> <input name="I1" num_pins="2" equivalent="none"/>
<input name="I1i" num_pins="2" equivalent="none"/> <input name="I1i" num_pins="2" equivalent="none"/>
<input name="I2" num_pins="2" equivalent="full"/> <input name="I2" num_pins="2" equivalent="none"/>
<input name="I2i" num_pins="2" equivalent="none"/> <input name="I2i" num_pins="2" equivalent="none"/>
<input name="I3" num_pins="2" equivalent="full"/> <input name="I3" num_pins="2" equivalent="none"/>
<input name="I3i" num_pins="2" equivalent="none"/> <input name="I3i" num_pins="2" equivalent="none"/>
<input name="I4" num_pins="2" equivalent="full"/> <input name="I4" num_pins="2" equivalent="none"/>
<input name="I4i" num_pins="2" equivalent="none"/> <input name="I4i" num_pins="2" equivalent="none"/>
<input name="I5" num_pins="2" equivalent="full"/> <input name="I5" num_pins="2" equivalent="none"/>
<input name="I5i" num_pins="2" equivalent="none"/> <input name="I5i" num_pins="2" equivalent="none"/>
<input name="I6" num_pins="2" equivalent="full"/> <input name="I6" num_pins="2" equivalent="none"/>
<input name="I6i" num_pins="2" equivalent="none"/> <input name="I6i" num_pins="2" equivalent="none"/>
<input name="I7" num_pins="2" equivalent="full"/> <input name="I7" num_pins="2" equivalent="none"/>
<input name="I7i" num_pins="2" equivalent="none"/> <input name="I7i" num_pins="2" equivalent="none"/>
<input name="reg_in" num_pins="1"/> <input name="reg_in" num_pins="1"/>
<input name="sc_in" num_pins="1"/> <input name="sc_in" num_pins="1"/>
@ -507,9 +507,8 @@
</direct> </direct>
<direct name="direct5" input="adder_lut4.lut4_out" output="soft_adder.sumout[0:0]"> <direct name="direct5" input="adder_lut4.lut4_out" output="soft_adder.sumout[0:0]">
</direct> </direct>
<!-- The MUX may not be needed once we limit the number of inputs of adder_lut4 to be 2 --> <direct name="direct6" input="soft_adder.in[2:2]" output="adder_lut4.in[2:2]">
<mux name="mux1" input="soft_adder.cin soft_adder.in[2:2]" output="adder_lut4.in[2:2]"> </direct>
</mux>
</interconnect> </interconnect>
</pb_type> </pb_type>
<interconnect> <interconnect>