From ad25944e59ddaf2f25ea194e9766de0f60536f86 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 23 Feb 2021 19:00:27 -0700
Subject: [PATCH] [Arch] Patched superLUT architecture example when trying
 adder8 synthesis script

---
 ...n_chain_nonLR_caravel_io_skywater130nm.xml | 45 +++++++++----------
 1 file changed, 22 insertions(+), 23 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index 3d71ffff9..17e37ee04 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -125,21 +125,21 @@
       <equivalent_sites>
         <site pb_type="clb"/>
       </equivalent_sites>
-      <input name="I0" num_pins="2" equivalent="full"/>
+      <input name="I0" num_pins="2" equivalent="none"/>
       <input name="I0i" num_pins="2" equivalent="none"/>
-      <input name="I1" num_pins="2" equivalent="full"/>
+      <input name="I1" num_pins="2" equivalent="none"/>
       <input name="I1i" num_pins="2" equivalent="none"/>
-      <input name="I2" num_pins="2" equivalent="full"/>
+      <input name="I2" num_pins="2" equivalent="none"/>
       <input name="I2i" num_pins="2" equivalent="none"/>
-      <input name="I3" num_pins="2" equivalent="full"/>
+      <input name="I3" num_pins="2" equivalent="none"/>
       <input name="I3i" num_pins="2" equivalent="none"/>
-      <input name="I4" num_pins="2" equivalent="full"/>
+      <input name="I4" num_pins="2" equivalent="none"/>
       <input name="I4i" num_pins="2" equivalent="none"/>
-      <input name="I5" num_pins="2" equivalent="full"/>
+      <input name="I5" num_pins="2" equivalent="none"/>
       <input name="I5i" num_pins="2" equivalent="none"/>
-      <input name="I6" num_pins="2" equivalent="full"/>
+      <input name="I6" num_pins="2" equivalent="none"/>
       <input name="I6i" num_pins="2" equivalent="none"/>
-      <input name="I7" num_pins="2" equivalent="full"/>
+      <input name="I7" num_pins="2" equivalent="none"/>
       <input name="I7i" num_pins="2" equivalent="none"/>
       <input name="reg_in" num_pins="1"/>
       <input name="sc_in" num_pins="1"/>
@@ -333,27 +333,27 @@
     </pb_type>
     <!-- Define I/O pads ends -->
     <!-- Define general purpose logic block (CLB) begin -->
-    <!-- -Due to the absence of local routing, 
-         the 4 inputs of fracturable LUT4 are no longer equivalent, 
-         because the 4th input can not be switched when the dual-LUT3 modes are used.
-         So pin equivalence should be applied to the first 3 inputs only
+    <!-- Due to that LUT bitstream may be overwritten by .eblif files
+         Pin equivalence of CLB inputs are all disabled.
+         This is because the hard coded bitstream in .eblif cannot be
+         adapted to the net swapping from VPR's routing optimization
 	  -->
     <pb_type name="clb">
-      <input name="I0" num_pins="2" equivalent="full"/>
+      <input name="I0" num_pins="2" equivalent="none"/>
       <input name="I0i" num_pins="2" equivalent="none"/>
-      <input name="I1" num_pins="2" equivalent="full"/>
+      <input name="I1" num_pins="2" equivalent="none"/>
       <input name="I1i" num_pins="2" equivalent="none"/>
-      <input name="I2" num_pins="2" equivalent="full"/>
+      <input name="I2" num_pins="2" equivalent="none"/>
       <input name="I2i" num_pins="2" equivalent="none"/>
-      <input name="I3" num_pins="2" equivalent="full"/>
+      <input name="I3" num_pins="2" equivalent="none"/>
       <input name="I3i" num_pins="2" equivalent="none"/>
-      <input name="I4" num_pins="2" equivalent="full"/>
+      <input name="I4" num_pins="2" equivalent="none"/>
       <input name="I4i" num_pins="2" equivalent="none"/>
-      <input name="I5" num_pins="2" equivalent="full"/>
+      <input name="I5" num_pins="2" equivalent="none"/>
       <input name="I5i" num_pins="2" equivalent="none"/>
-      <input name="I6" num_pins="2" equivalent="full"/>
+      <input name="I6" num_pins="2" equivalent="none"/>
       <input name="I6i" num_pins="2" equivalent="none"/>
-      <input name="I7" num_pins="2" equivalent="full"/>
+      <input name="I7" num_pins="2" equivalent="none"/>
       <input name="I7i" num_pins="2" equivalent="none"/>
       <input name="reg_in" num_pins="1"/>
       <input name="sc_in" num_pins="1"/>
@@ -507,9 +507,8 @@
               </direct>
               <direct name="direct5" input="adder_lut4.lut4_out" output="soft_adder.sumout[0:0]">
               </direct>
-              <!-- The MUX may not be needed once we limit the number of inputs of adder_lut4 to be 2 -->
-              <mux name="mux1" input="soft_adder.cin soft_adder.in[2:2]" output="adder_lut4.in[2:2]">
-              </mux>
+              <direct name="direct6" input="soft_adder.in[2:2]" output="adder_lut4.in[2:2]">
+              </direct>
             </interconnect>
           </pb_type>
           <interconnect>