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[core] rework the option 'constant_undriven_inputs'

This commit is contained in:
tangxifan 2024-08-06 16:50:49 -07:00
parent 41160bb2c3
commit ac2337d24b
16 changed files with 168 additions and 88 deletions
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7
openfpga/src/base/openfpga_verilog_command_template.h
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@ -31,10 +31,11 @@ ShellCommandId add_write_fabric_verilog_command_template(
shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING); shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
/* Add an option '--constant_undriven_inputs' */ /* Add an option '--constant_undriven_inputs' */
shell_cmd.add_option( CommandOptionId const_undriven_inputs_opt = shell_cmd.add_option(
"constant_undriven_inputs", false, "constant_undriven_inputs", true,
"Use constant gnd for undriven wires in Verilog netlists. Recommand to " "Can be [none|bus0|bus1|bit0|bit1]. Use constant vdd/gnd for undriven wires in Verilog netlists. Recommand to "
"enable when there are boundary routing tracks in FPGA fabric"); "enable when there are boundary routing tracks in FPGA fabric");
shell_cmd.set_option_require_value(const_undriven_inputs_opt, openfpga::OPT_STRING);
/* Add an option '--explicit_port_mapping' */ /* Add an option '--explicit_port_mapping' */
shell_cmd.add_option("explicit_port_mapping", false, shell_cmd.add_option("explicit_port_mapping", false,

20
openfpga/src/base/openfpga_verilog_template.h
View File

@ -58,16 +58,18 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
} }
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose)); options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing()); options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
/* For perimeter cb, enable the constant undriven inputs, unless it is off by /* For perimeter cb, enable the constant-zero undriven inputs, unless it is defined by
* user */ * user. Throw error if the constant inputs are not selected! */
if (cmd_context.option_enable(cmd, opt_constant_undriven_inputs)) {
options.set_constant_undriven_inputs(cmd_context.option_value(cmd, opt_constant_undriven_inputs));
}
if (g_vpr_ctx.device().arch->perimeter_cb) { if (g_vpr_ctx.device().arch->perimeter_cb) {
options.set_constant_undriven_inputs(true); if (FabricVerilogOptions::e_undriven_input_type::NONE == options.constant_undriven_inputs()) {
VTR_LOG( options.set_constant_undriven_inputs(FabricVerilogOptions::e_undriven_input_type::BUS0);
"Automatically enable the constant_undriven_input option as perimeter " VTR_LOG(
"connection blocks are seen in FPGA fabric\n"); "Automatically enable the constant_undriven_input option as perimeter "
} else { "connection blocks are seen in FPGA fabric\n");
options.set_constant_undriven_inputs( }
cmd_context.option_enable(cmd, opt_constant_undriven_inputs));
} }
return fpga_fabric_verilog( return fpga_fabric_verilog(

48
openfpga/src/fpga_verilog/fabric_verilog_options.cpp
View File

@ -21,7 +21,8 @@ FabricVerilogOption::FabricVerilogOption() {
default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE; default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
time_stamp_ = true; time_stamp_ = true;
use_relative_path_ = false; use_relative_path_ = false;
constant_undriven_inputs_ = false; constant_undriven_inputs_ = FabricVerilogOption::e_undriven_input_type::NONE;
CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_ = {"none", "bus0", "bus1", "bit0", "bit1"};
verbose_output_ = false; verbose_output_ = false;
} }
@ -54,10 +55,33 @@ e_verilog_default_net_type FabricVerilogOption::default_net_type() const {
return default_net_type_; return default_net_type_;
} }
bool FabricVerilogOption::constant_undriven_inputs() const { FabricVerilogOption::e_undriven_input_type FabricVerilogOption::constant_undriven_inputs() const {
return constant_undriven_inputs_; return constant_undriven_inputs_;
} }
bool FabricVerilogOption::constant_undriven_inputs_use_bus() const {
return constant_undriven_inputs_ == FabricVerilogOption::e_undriven_input_type::BUS0
|| constant_undriven_inputs_ == FabricVerilogOption::e_undriven_input_type::BUS1;
}
size_t FabricVerilogOption::constant_undriven_inputs_value() const {
if (constant_undriven_inputs_ == FabricVerilogOption::e_undriven_input_type::BUS1
|| constant_undriven_inputs_ == FabricVerilogOption::e_undriven_input_type::BIT1) {
return 1;
}
return 0;
}
std::string FabricVerilogOption::full_constant_undriven_input_type_str() const;
std::string full_type_str("[");
for (size_t itype = 0; itype < FabricVerilogOption::e_undriven_input_type::NUM_TYPES; ++itype) {
full_type_str += std::string(CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_[itype]) + std::string("|");
}
full_type_str.pop_back();
full_type_str += std::string("]");
return full_type_str;
}
bool FabricVerilogOption::verbose_output() const { return verbose_output_; } bool FabricVerilogOption::verbose_output() const { return verbose_output_; }
/****************************************************************************** /******************************************************************************
@ -111,8 +135,24 @@ void FabricVerilogOption::set_default_net_type(
} }
} }
void FabricVerilogOption::set_constant_undriven_inputs(const bool& enabled) { bool FabricVerilogOption::set_constant_undriven_inputs(const std::string& type_str) {
constant_undriven_inputs_ = enabled; bool valid_type = false;
for (size_t itype = 0; itype < FabricVerilogOption::e_undriven_input_type::NUM_TYPES; ++itype) {
if (std::string(CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_[itype]) == type_str) {
constant_undriven_inputs_ = static_cast<FabricVerilogOption::e_undriven_input_type>(itype);
valid_type = true;
break;
}
}
if (!valid_type) {
VTR_LOG_ERROR("Invalid types for undriven inputs: %s. Expect %s\n", type_str.c_str(), full_constant_undriven_input_type_str().c_str());
}
return valid_type;
}
bool FabricVerilogOption::set_constant_undriven_inputs(const FabricVerilogOption::e_undriven_input_type& type) {
constant_undriven_inputs_ = type;
return type != FabricVerilogOption::e_undriven_input_type::NUM_TYPES;
} }
void FabricVerilogOption::set_verbose_output(const bool& enabled) { void FabricVerilogOption::set_verbose_output(const bool& enabled) {

27
openfpga/src/fpga_verilog/fabric_verilog_options.h
View File

@ -15,6 +15,15 @@ namespace openfpga {
* Options for Fabric Verilog generator * Options for Fabric Verilog generator
*******************************************************************/ *******************************************************************/
class FabricVerilogOption { class FabricVerilogOption {
public: /* Types */
enum class e_undriven_input_type {
NONE = 0, /* Leave undriven input to be dangling */
BUS0, /* Wire to a bus format of constant 0 */
BUS1, /* Wire to a bus format of constant 1 */
BIT0, /* Wire to a blast-bit format of constant 0 */
BIT1, /* Wire to a blast-bit format of constant 1 */
NUM_TYPES
};
public: /* Public constructor */ public: /* Public constructor */
/* Set default options */ /* Set default options */
FabricVerilogOption(); FabricVerilogOption();
@ -28,7 +37,12 @@ class FabricVerilogOption {
bool compress_routing() const; bool compress_routing() const;
e_verilog_default_net_type default_net_type() const; e_verilog_default_net_type default_net_type() const;
bool print_user_defined_template() const; bool print_user_defined_template() const;
bool constant_undriven_inputs() const; e_undriven_input_type constant_undriven_inputs() const;
/* Identify if a bus format should be applied when wiring undriven inputs to constants */
bool constant_undriven_inputs_use_bus() const;
/* Identify the logic value should be applied when wiring undriven inputs to constants */
size_t constant_undriven_inputs_value() const;
std::string full_constant_undriven_input_type_str() const;
bool verbose_output() const; bool verbose_output() const;
public: /* Public mutators */ public: /* Public mutators */
@ -40,7 +54,13 @@ class FabricVerilogOption {
void set_compress_routing(const bool& enabled); void set_compress_routing(const bool& enabled);
void set_print_user_defined_template(const bool& enabled); void set_print_user_defined_template(const bool& enabled);
void set_default_net_type(const std::string& default_net_type); void set_default_net_type(const std::string& default_net_type);
void set_constant_undriven_inputs(const bool& enabled); /** Decode the type from string to enumeration
* "none" -> NONE, "bus0" -> BUS0, "bus1" -> BUS1, "bit0" -> BIT0, "bit1" -> BIT1
* For invalid types, error out
*/
bool set_constant_undriven_inputs(const std::string& type_str);
/** For invalid types, error out */
bool set_constant_undriven_inputs(const e_undriven_input_type& type);
void set_verbose_output(const bool& enabled); void set_verbose_output(const bool& enabled);
private: /* Internal Data */ private: /* Internal Data */
@ -52,7 +72,8 @@ class FabricVerilogOption {
e_verilog_default_net_type default_net_type_; e_verilog_default_net_type default_net_type_;
bool time_stamp_; bool time_stamp_;
bool use_relative_path_; bool use_relative_path_;
bool constant_undriven_inputs_; e_undriven_input_type constant_undriven_inputs_;
std::array<const char*, FabricVerilogOption::e_undriven_input_type::NUM_TYPES> CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_; //String versions of constant undriven input types
bool verbose_output_; bool verbose_output_;
}; };

12
openfpga/src/fpga_verilog/verilog_grid.cpp
View File

@ -113,9 +113,9 @@ static void print_verilog_primitive_block(
module_manager.module_name(primitive_module).c_str()); module_manager.module_name(primitive_module).c_str());
/* Write the verilog module */ /* Write the verilog module */
write_verilog_module_to_file(fp, module_manager, primitive_module, true, FabricVerilogOption curr_options = options;
options.constant_undriven_inputs(), curr_options.set_explicit_port_mapping(true);
options.default_net_type()); write_verilog_module_to_file(fp, module_manager, primitive_module, curr_options);
/* Close file handler */ /* Close file handler */
fp.close(); fp.close();
@ -234,8 +234,7 @@ static void rec_print_verilog_logical_tile(
/* Write the verilog module */ /* Write the verilog module */
write_verilog_module_to_file( write_verilog_module_to_file(
fp, module_manager, pb_module, options.explicit_port_mapping(), fp, module_manager, pb_module, options);
options.constant_undriven_inputs(), options.default_net_type());
print_verilog_comment( print_verilog_comment(
fp, fp,
@ -348,8 +347,7 @@ static void print_verilog_physical_tile_netlist(
fp, std::string("----- BEGIN Grid Verilog module: " + fp, std::string("----- BEGIN Grid Verilog module: " +
module_manager.module_name(grid_module) + " -----")); module_manager.module_name(grid_module) + " -----"));
write_verilog_module_to_file( write_verilog_module_to_file(
fp, module_manager, grid_module, options.explicit_port_mapping(), fp, module_manager, grid_module, options);
options.constant_undriven_inputs(), options.default_net_type());
print_verilog_comment( print_verilog_comment(
fp, std::string("----- END Grid Verilog module: " + fp, std::string("----- END Grid Verilog module: " +

9
openfpga/src/fpga_verilog/verilog_lut.cpp
View File

@ -59,11 +59,12 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
ModuleId lut_module = module_manager.find_module( ModuleId lut_module = module_manager.find_module(
module_name_map.name(circuit_lib.model_name(lut_model))); module_name_map.name(circuit_lib.model_name(lut_model)));
VTR_ASSERT(true == module_manager.valid_module_id(lut_module)); VTR_ASSERT(true == module_manager.valid_module_id(lut_module));
write_verilog_module_to_file( FabricVerilogOption curr_options = options;
fp, module_manager, lut_module, curr_options.set_explicit_port_mapping(
options.explicit_port_mapping() || options.explicit_port_mapping() ||
circuit_lib.dump_explicit_port_map(lut_model), circuit_lib.dump_explicit_port_map(lut_model));
options.constant_undriven_inputs(), options.default_net_type()); write_verilog_module_to_file(
fp, module_manager, lut_module, curr_options);
} }
/* Close the file handler */ /* Close the file handler */

32
openfpga/src/fpga_verilog/verilog_memory.cpp
View File

@ -57,11 +57,12 @@ static void print_verilog_mux_memory_module(
ModuleId mem_module = module_manager.find_module(module_name); ModuleId mem_module = module_manager.find_module(module_name);
VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
/* Write the module content in Verilog format */ /* Write the module content in Verilog format */
write_verilog_module_to_file( FabricVerilogOption curr_options = options;
fp, module_manager, mem_module, curr_options.set_explicit_port_mapping(
options.explicit_port_mapping() || options.explicit_port_mapping() ||
circuit_lib.dump_explicit_port_map(mux_model), circuit_lib.dump_explicit_port_map(mux_model));
options.constant_undriven_inputs(), options.default_net_type()); write_verilog_module_to_file(
fp, module_manager, mem_module, curr_options);
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;
@ -81,10 +82,7 @@ static void print_verilog_mux_memory_module(
VTR_ASSERT(true == module_manager.valid_module_id(feedthru_mem_module)); VTR_ASSERT(true == module_manager.valid_module_id(feedthru_mem_module));
/* Write the module content in Verilog format */ /* Write the module content in Verilog format */
write_verilog_module_to_file( write_verilog_module_to_file(
fp, module_manager, feedthru_mem_module, fp, module_manager, feedthru_mem_module, curr_options);
options.explicit_port_mapping() ||
circuit_lib.dump_explicit_port_map(mux_model),
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;
@ -205,11 +203,11 @@ void print_verilog_submodule_memories(
ModuleId mem_module = module_manager.find_module(module_name); ModuleId mem_module = module_manager.find_module(module_name);
VTR_ASSERT(true == module_manager.valid_module_id(mem_module)); VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
/* Write the module content in Verilog format */ /* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, mem_module, FabricVerilogOption curr_options = options;
options.explicit_port_mapping() || curr_options.set_explicit_port_mapping(
circuit_lib.dump_explicit_port_map(model), options.explicit_port_mapping() ||
options.constant_undriven_inputs(), circuit_lib.dump_explicit_port_map(model));
options.default_net_type()); write_verilog_module_to_file(fp, module_manager, mem_module, curr_options);
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;
@ -227,10 +225,7 @@ void print_verilog_submodule_memories(
if (module_manager.valid_module_id(feedthru_mem_module)) { if (module_manager.valid_module_id(feedthru_mem_module)) {
/* Write the module content in Verilog format */ /* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, feedthru_mem_module, write_verilog_module_to_file(fp, module_manager, feedthru_mem_module,
options.explicit_port_mapping() || curr_options);
circuit_lib.dump_explicit_port_map(model),
options.constant_undriven_inputs(),
options.default_net_type());
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;
@ -242,8 +237,7 @@ void print_verilog_submodule_memories(
ModuleManager::e_module_usage_type::MODULE_CONFIG_GROUP)) { ModuleManager::e_module_usage_type::MODULE_CONFIG_GROUP)) {
/* Write the module content in Verilog format */ /* Write the module content in Verilog format */
write_verilog_module_to_file( write_verilog_module_to_file(
fp, module_manager, mem_group_module, options.explicit_port_mapping(), fp, module_manager, mem_group_module, options);
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;

27
openfpga/src/fpga_verilog/verilog_module_writer.cpp
View File

@ -572,9 +572,8 @@ static void write_verilog_instance_to_file(std::fstream& fp,
*******************************************************************/ *******************************************************************/
void write_verilog_module_to_file( void write_verilog_module_to_file(
std::fstream& fp, const ModuleManager& module_manager, std::fstream& fp, const ModuleManager& module_manager,
const ModuleId& module_id, const bool& use_explicit_port_map, const ModuleId& module_id,
const bool& constant_local_undriven_wires, const FabricVerilogOption& options) {
const e_verilog_default_net_type& default_net_type) {
VTR_ASSERT(true == valid_file_stream(fp)); VTR_ASSERT(true == valid_file_stream(fp));
/* Ensure we have a valid module_id */ /* Ensure we have a valid module_id */
@ -582,7 +581,7 @@ void write_verilog_module_to_file(
/* Print module declaration */ /* Print module declaration */
print_verilog_module_declaration(fp, module_manager, module_id, print_verilog_module_declaration(fp, module_manager, module_id,
default_net_type); options.default_net_type());
/* Print an empty line as splitter */ /* Print an empty line as splitter */
fp << std::endl; fp << std::endl;
@ -595,7 +594,7 @@ void write_verilog_module_to_file(
for (const BasicPort& local_wire : port_group.second) { for (const BasicPort& local_wire : port_group.second) {
/* When default net type is wire, we can skip single-bit wires whose LSB /* When default net type is wire, we can skip single-bit wires whose LSB
* is 0 */ * is 0 */
if ((VERILOG_DEFAULT_NET_TYPE_WIRE == default_net_type) && if ((VERILOG_DEFAULT_NET_TYPE_WIRE == options.default_net_type()) &&
(1 == local_wire.get_width()) && (0 == local_wire.get_lsb())) { (1 == local_wire.get_width()) && (0 == local_wire.get_lsb())) {
continue; continue;
} }
@ -605,7 +604,7 @@ void write_verilog_module_to_file(
} }
/* Use constant to drive undriven local wires */ /* Use constant to drive undriven local wires */
if (constant_local_undriven_wires) { if (options.constant_local_undriven_inputs() != FabricVerilogOption::e_undriven_input_type::NONE) {
std::vector<ModuleManager::e_module_port_type> blacklist = { std::vector<ModuleManager::e_module_port_type> blacklist = {
ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT, ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT,
ModuleManager::e_module_port_type::MODULE_GPIN_PORT, ModuleManager::e_module_port_type::MODULE_GPIN_PORT,
@ -620,9 +619,15 @@ void write_verilog_module_to_file(
for (std::pair<std::string, std::vector<BasicPort>> port_group : for (std::pair<std::string, std::vector<BasicPort>> port_group :
local_undriven_wires) { local_undriven_wires) {
for (const BasicPort& local_undriven_wire : port_group.second) { for (const BasicPort& local_undriven_wire : port_group.second) {
print_verilog_wire_constant_values( if (options.constant_local_undriven_inputs_use_bus()) {
fp, local_undriven_wire, print_verilog_wire_constant_values(
std::vector<size_t>(local_undriven_wire.get_width(), 0)); fp, local_undriven_wire,
std::vector<size_t>(local_undriven_wire.get_width(), options.constant_local_undriven_inputs_value()));
} else {
print_verilog_wire_constant_values_bit_blast(
fp, local_undriven_wire,
std::vector<size_t>(local_undriven_wire.get_width(), options.constant_local_undriven_inputs_value()));
}
} }
} }
} }
@ -653,7 +658,7 @@ void write_verilog_module_to_file(
/* Print an instance */ /* Print an instance */
write_verilog_instance_to_file(fp, module_manager, module_id, write_verilog_instance_to_file(fp, module_manager, module_id,
child_module, instance, child_module, instance,
use_explicit_port_map); options.use_explicit_port_map());
/* Print an empty line as splitter */ /* Print an empty line as splitter */
fp << std::endl; fp << std::endl;
} }
@ -661,7 +666,7 @@ void write_verilog_module_to_file(
/* Print an end for the module */ /* Print an end for the module */
print_verilog_module_end(fp, module_manager.module_name(module_id), print_verilog_module_end(fp, module_manager.module_name(module_id),
default_net_type); options.default_net_type());
/* Print an empty line as splitter */ /* Print an empty line as splitter */
fp << std::endl; fp << std::endl;

6
openfpga/src/fpga_verilog/verilog_module_writer.h
View File

@ -8,6 +8,7 @@
#include "module_manager.h" #include "module_manager.h"
#include "verilog_port_types.h" #include "verilog_port_types.h"
#include "fabric_verilog_options.h"
/******************************************************************** /********************************************************************
* Function declaration * Function declaration
@ -18,9 +19,8 @@ namespace openfpga {
void write_verilog_module_to_file( void write_verilog_module_to_file(
std::fstream& fp, const ModuleManager& module_manager, std::fstream& fp, const ModuleManager& module_manager,
const ModuleId& module_id, const bool& use_explicit_port_map, const ModuleId& module_id,
const bool& constant_local_undriven_wires, const FabricVerilogOption& options);
const e_verilog_default_net_type& default_net_type);
} /* end namespace openfpga */ } /* end namespace openfpga */

27
openfpga/src/fpga_verilog/verilog_mux.cpp
View File

@ -643,8 +643,7 @@ static void generate_verilog_rram_mux_branch_module(
static void generate_verilog_mux_branch_module( static void generate_verilog_mux_branch_module(
ModuleManager& module_manager, const CircuitLibrary& circuit_lib, ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph, std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph,
const ModuleNameMap& module_name_map, const bool& use_explicit_port_map, const ModuleNameMap& module_name_map, const FabricVerilogOption& options,
const e_verilog_default_net_type& default_net_type,
std::map<std::string, bool>& branch_mux_module_is_outputted) { std::map<std::string, bool>& branch_mux_module_is_outputted) {
std::string module_name = generate_mux_branch_subckt_name( std::string module_name = generate_mux_branch_subckt_name(
circuit_lib, mux_model, mux_graph.num_inputs(), mux_graph.num_memory_bits(), circuit_lib, mux_model, mux_graph.num_inputs(), mux_graph.num_memory_bits(),
@ -675,11 +674,14 @@ static void generate_verilog_mux_branch_module(
/* Structural verilog can be easily generated by module writer */ /* Structural verilog can be easily generated by module writer */
ModuleId mux_module = module_manager.find_module(module_name); ModuleId mux_module = module_manager.find_module(module_name);
VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
FabricVerilogOption curr_options = options;
curr_options.set_explicit_port_mapping(
use_explicit_port_map ||
circuit_lib.dump_explicit_port_map(mux_model));
curr_options.set_constant_undriven_inputs(FabricVerilogOption::e_undriven_input_type::NONE);
write_verilog_module_to_file( write_verilog_module_to_file(
fp, module_manager, mux_module, fp, module_manager, mux_module,
use_explicit_port_map || curr_options);
circuit_lib.dump_explicit_port_map(mux_model),
false, default_net_type);
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;
} else { } else {
@ -1417,13 +1419,17 @@ static void generate_verilog_mux_module(
/* Use Verilog writer to print the module to file */ /* Use Verilog writer to print the module to file */
ModuleId mux_module = module_manager.find_module(module_name); ModuleId mux_module = module_manager.find_module(module_name);
VTR_ASSERT(true == module_manager.valid_module_id(mux_module)); VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
write_verilog_module_to_file( FabricVerilogOption curr_options = options;
fp, module_manager, mux_module, curr_option.set_explict_port_mapping(
(use_explicit_port_map || (use_explicit_port_map ||
circuit_lib.dump_explicit_port_map(mux_model) || circuit_lib.dump_explicit_port_map(mux_model) ||
circuit_lib.dump_explicit_port_map( circuit_lib.dump_explicit_port_map(
circuit_lib.pass_gate_logic_model(mux_model))), circuit_lib.pass_gate_logic_model(mux_model)))
false, default_net_type); );
curr_option.set_constant_undriven_inputs(FabricVerilogOption::e_undriven_input_type::NONE);
write_verilog_module_to_file(
fp, module_manager, mux_module,
curr_options);
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;
break; break;
@ -1486,8 +1492,7 @@ static void print_verilog_submodule_mux_primitives(
for (auto branch_mux_graph : branch_mux_graphs) { for (auto branch_mux_graph : branch_mux_graphs) {
generate_verilog_mux_branch_module( generate_verilog_mux_branch_module(
module_manager, circuit_lib, fp, mux_circuit_model, branch_mux_graph, module_manager, circuit_lib, fp, mux_circuit_model, branch_mux_graph,
module_name_map, options.explicit_port_mapping(), module_name_map, options, branch_mux_module_is_outputted);
options.default_net_type(), branch_mux_module_is_outputted);
} }
} }

6
openfpga/src/fpga_verilog/verilog_routing.cpp
View File

@ -116,8 +116,7 @@ static void print_verilog_routing_connection_box_unique_module(
/* Write the verilog module */ /* Write the verilog module */
write_verilog_module_to_file( write_verilog_module_to_file(
fp, module_manager, cb_module, options.explicit_port_mapping(), fp, module_manager, cb_module, options);
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;
@ -237,8 +236,7 @@ static void print_verilog_routing_switch_box_unique_module(
/* Write the verilog module */ /* Write the verilog module */
write_verilog_module_to_file( write_verilog_module_to_file(
fp, module_manager, sb_module, options.explicit_port_mapping(), fp, module_manager, sb_module, options);
options.constant_undriven_inputs(), options.default_net_type());
/* Close file handler */ /* Close file handler */
fp.close(); fp.close();

6
openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
View File

@ -57,8 +57,7 @@ void print_verilog_submodule_shift_register_banks(
VTR_ASSERT(true == module_manager.valid_module_id(sr_module)); VTR_ASSERT(true == module_manager.valid_module_id(sr_module));
/* Write the module content in Verilog format */ /* Write the module content in Verilog format */
write_verilog_module_to_file( write_verilog_module_to_file(
fp, module_manager, sr_module, options.explicit_port_mapping(), fp, module_manager, sr_module, options);
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;
@ -68,8 +67,7 @@ void print_verilog_submodule_shift_register_banks(
VTR_ASSERT(true == module_manager.valid_module_id(sr_module)); VTR_ASSERT(true == module_manager.valid_module_id(sr_module));
/* Write the module content in Verilog format */ /* Write the module content in Verilog format */
write_verilog_module_to_file( write_verilog_module_to_file(
fp, module_manager, sr_module, options.explicit_port_mapping(), fp, module_manager, sr_module, options);
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;

3
openfpga/src/fpga_verilog/verilog_tile.cpp
View File

@ -59,8 +59,7 @@ static int print_verilog_tile_module_netlist(
/* Write the module content in Verilog format */ /* Write the module content in Verilog format */
write_verilog_module_to_file( write_verilog_module_to_file(
fp, module_manager, tile_module, options.explicit_port_mapping(), fp, module_manager, tile_module, options);
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;

6
openfpga/src/fpga_verilog/verilog_top_module.cpp
View File

@ -62,8 +62,7 @@ void print_verilog_core_module(NetlistManager& netlist_manager,
/* Write the module content in Verilog format */ /* Write the module content in Verilog format */
write_verilog_module_to_file( write_verilog_module_to_file(
fp, module_manager, core_module, options.explicit_port_mapping(), fp, module_manager, core_module, options);
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;
@ -128,8 +127,7 @@ void print_verilog_top_module(NetlistManager& netlist_manager,
/* Write the module content in Verilog format */ /* Write the module content in Verilog format */
write_verilog_module_to_file( write_verilog_module_to_file(
fp, module_manager, top_module, options.explicit_port_mapping(), fp, module_manager, top_module, options);
options.constant_undriven_inputs(), options.default_net_type());
/* Add an empty line as a splitter */ /* Add an empty line as a splitter */
fp << std::endl; fp << std::endl;

16
openfpga/src/fpga_verilog/verilog_writer_utils.cpp
View File

@ -831,6 +831,22 @@ void print_verilog_wire_constant_values(
fp << ";" << std::endl; fp << ";" << std::endl;
} }
/********************************************************************
* Generate a wire connection, that assigns constant values to a
* Verilog port
*******************************************************************/
void print_verilog_wire_constant_values_bit_blast(
std::fstream& fp, const BasicPort& output_port,
const std::vector<size_t>& const_values) {
/* Make sure we have a valid file handler*/
VTR_ASSERT(true == valid_file_stream(fp));
for (size_t ipin : output_port.pins()) {
BasicPort curr_pin(output_port.get_name(), ipin, ipin);
print_verilog_wire_constant_values_bit_blast(fp, curr_pin, const_values[ipin]);
}
}
/******************************************************************** /********************************************************************
* Deposit constant values to a Verilog port * Deposit constant values to a Verilog port
*******************************************************************/ *******************************************************************/

4
openfpga/src/fpga_verilog/verilog_writer_utils.h
View File

@ -123,6 +123,10 @@ void print_verilog_wire_constant_values(
std::fstream& fp, const BasicPort& output_port, std::fstream& fp, const BasicPort& output_port,
const std::vector<size_t>& const_values); const std::vector<size_t>& const_values);
void print_verilog_wire_constant_values_bit_blast(
std::fstream& fp, const BasicPort& output_port,
const std::vector<size_t>& const_values);
void print_verilog_deposit_wire_constant_values( void print_verilog_deposit_wire_constant_values(
std::fstream& fp, const BasicPort& output_port, std::fstream& fp, const BasicPort& output_port,
const std::vector<size_t>& const_values); const std::vector<size_t>& const_values);