diff --git a/openfpga/src/base/openfpga_verilog_command_template.h b/openfpga/src/base/openfpga_verilog_command_template.h
index 001f7ee40..e2e1fabd1 100644
--- a/openfpga/src/base/openfpga_verilog_command_template.h
+++ b/openfpga/src/base/openfpga_verilog_command_template.h
@@ -31,10 +31,11 @@ ShellCommandId add_write_fabric_verilog_command_template(
   shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
 
   /* Add an option '--constant_undriven_inputs' */
-  shell_cmd.add_option(
-    "constant_undriven_inputs", false,
-    "Use constant gnd for undriven wires in Verilog netlists. Recommand to "
+  CommandOptionId const_undriven_inputs_opt = shell_cmd.add_option(
+    "constant_undriven_inputs", true,
+    "Can be [none|bus0|bus1|bit0|bit1]. Use constant vdd/gnd for undriven wires in Verilog netlists. Recommand to "
     "enable when there are boundary routing tracks in FPGA fabric");
+  shell_cmd.set_option_require_value(const_undriven_inputs_opt, openfpga::OPT_STRING);
 
   /* Add an option '--explicit_port_mapping' */
   shell_cmd.add_option("explicit_port_mapping", false,
diff --git a/openfpga/src/base/openfpga_verilog_template.h b/openfpga/src/base/openfpga_verilog_template.h
index 93dc8035a..4545b3eeb 100644
--- a/openfpga/src/base/openfpga_verilog_template.h
+++ b/openfpga/src/base/openfpga_verilog_template.h
@@ -58,16 +58,18 @@ int write_fabric_verilog_template(T& openfpga_ctx, const Command& cmd,
   }
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
   options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
-  /* For perimeter cb, enable the constant undriven inputs, unless it is off by
-   * user */
+  /* For perimeter cb, enable the constant-zero undriven inputs, unless it is defined by
+   * user. Throw error if the constant inputs are not selected! */
+  if (cmd_context.option_enable(cmd, opt_constant_undriven_inputs)) {
+    options.set_constant_undriven_inputs(cmd_context.option_value(cmd, opt_constant_undriven_inputs));
+  }
   if (g_vpr_ctx.device().arch->perimeter_cb) {
-    options.set_constant_undriven_inputs(true);
-    VTR_LOG(
-      "Automatically enable the constant_undriven_input option as perimeter "
-      "connection blocks are seen in FPGA fabric\n");
-  } else {
-    options.set_constant_undriven_inputs(
-      cmd_context.option_enable(cmd, opt_constant_undriven_inputs));
+    if (FabricVerilogOptions::e_undriven_input_type::NONE == options.constant_undriven_inputs()) {
+      options.set_constant_undriven_inputs(FabricVerilogOptions::e_undriven_input_type::BUS0);
+      VTR_LOG(
+        "Automatically enable the constant_undriven_input option as perimeter "
+        "connection blocks are seen in FPGA fabric\n");
+    }
   }
 
   return fpga_fabric_verilog(
diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
index 23f6aef12..a3b29f71e 100644
--- a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
@@ -21,7 +21,8 @@ FabricVerilogOption::FabricVerilogOption() {
   default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
   time_stamp_ = true;
   use_relative_path_ = false;
-  constant_undriven_inputs_ = false;
+  constant_undriven_inputs_ = FabricVerilogOption::e_undriven_input_type::NONE;
+  CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_ = {"none", "bus0", "bus1", "bit0", "bit1"};
   verbose_output_ = false;
 }
 
@@ -54,10 +55,33 @@ e_verilog_default_net_type FabricVerilogOption::default_net_type() const {
   return default_net_type_;
 }
 
-bool FabricVerilogOption::constant_undriven_inputs() const {
+FabricVerilogOption::e_undriven_input_type FabricVerilogOption::constant_undriven_inputs() const {
   return constant_undriven_inputs_;
 }
 
+bool FabricVerilogOption::constant_undriven_inputs_use_bus() const {
+  return constant_undriven_inputs_ == FabricVerilogOption::e_undriven_input_type::BUS0
+       || constant_undriven_inputs_ == FabricVerilogOption::e_undriven_input_type::BUS1;
+}
+
+size_t FabricVerilogOption::constant_undriven_inputs_value() const {
+  if (constant_undriven_inputs_ == FabricVerilogOption::e_undriven_input_type::BUS1
+       || constant_undriven_inputs_ == FabricVerilogOption::e_undriven_input_type::BIT1) {
+    return 1;
+  }
+  return 0;
+}
+
+std::string FabricVerilogOption::full_constant_undriven_input_type_str() const;
+  std::string full_type_str("[");
+  for (size_t itype = 0; itype < FabricVerilogOption::e_undriven_input_type::NUM_TYPES; ++itype) {
+    full_type_str += std::string(CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_[itype]) + std::string("|");
+  }
+  full_type_str.pop_back();
+  full_type_str += std::string("]");
+  return full_type_str;
+}
+
 bool FabricVerilogOption::verbose_output() const { return verbose_output_; }
 
 /******************************************************************************
@@ -111,8 +135,24 @@ void FabricVerilogOption::set_default_net_type(
   }
 }
 
-void FabricVerilogOption::set_constant_undriven_inputs(const bool& enabled) {
-  constant_undriven_inputs_ = enabled;
+bool FabricVerilogOption::set_constant_undriven_inputs(const std::string& type_str) {
+  bool valid_type = false;
+  for (size_t itype = 0; itype < FabricVerilogOption::e_undriven_input_type::NUM_TYPES; ++itype) {
+    if (std::string(CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_[itype]) == type_str) {
+      constant_undriven_inputs_ = static_cast<FabricVerilogOption::e_undriven_input_type>(itype);
+      valid_type = true;
+      break;
+    }
+  }
+  if (!valid_type) {
+    VTR_LOG_ERROR("Invalid types for undriven inputs: %s. Expect %s\n", type_str.c_str(), full_constant_undriven_input_type_str().c_str());
+  }
+  return valid_type;
+}
+
+bool FabricVerilogOption::set_constant_undriven_inputs(const FabricVerilogOption::e_undriven_input_type& type) {
+  constant_undriven_inputs_ = type;
+  return type != FabricVerilogOption::e_undriven_input_type::NUM_TYPES;
 }
 
 void FabricVerilogOption::set_verbose_output(const bool& enabled) {
diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.h b/openfpga/src/fpga_verilog/fabric_verilog_options.h
index c8d5cc5eb..1271277e0 100644
--- a/openfpga/src/fpga_verilog/fabric_verilog_options.h
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.h
@@ -15,6 +15,15 @@ namespace openfpga {
  * Options for Fabric Verilog generator
  *******************************************************************/
 class FabricVerilogOption {
+ public: /* Types */
+   enum class e_undriven_input_type {
+     NONE = 0, /* Leave undriven input to be dangling */
+     BUS0, /* Wire to a bus format of constant 0 */
+     BUS1, /* Wire to a bus format of constant 1 */
+     BIT0, /* Wire to a blast-bit format of constant 0 */
+     BIT1, /* Wire to a blast-bit format of constant 1 */
+     NUM_TYPES
+   };
  public: /* Public constructor */
   /* Set default options */
   FabricVerilogOption();
@@ -28,7 +37,12 @@ class FabricVerilogOption {
   bool compress_routing() const;
   e_verilog_default_net_type default_net_type() const;
   bool print_user_defined_template() const;
-  bool constant_undriven_inputs() const;
+  e_undriven_input_type constant_undriven_inputs() const;
+  /* Identify if a bus format should be applied when wiring undriven inputs to constants */
+  bool constant_undriven_inputs_use_bus() const;
+  /* Identify the logic value should be applied when wiring undriven inputs to constants */
+  size_t constant_undriven_inputs_value() const;
+  std::string full_constant_undriven_input_type_str() const;
   bool verbose_output() const;
 
  public: /* Public mutators */
@@ -40,7 +54,13 @@ class FabricVerilogOption {
   void set_compress_routing(const bool& enabled);
   void set_print_user_defined_template(const bool& enabled);
   void set_default_net_type(const std::string& default_net_type);
-  void set_constant_undriven_inputs(const bool& enabled);
+  /** Decode the type from string to enumeration 
+   * "none" -> NONE, "bus0" -> BUS0, "bus1" -> BUS1, "bit0" -> BIT0, "bit1" -> BIT1
+   * For invalid types, error out
+   */
+  bool set_constant_undriven_inputs(const std::string& type_str);
+  /** For invalid types, error out */
+  bool set_constant_undriven_inputs(const e_undriven_input_type& type);
   void set_verbose_output(const bool& enabled);
 
  private: /* Internal Data */
@@ -52,7 +72,8 @@ class FabricVerilogOption {
   e_verilog_default_net_type default_net_type_;
   bool time_stamp_;
   bool use_relative_path_;
-  bool constant_undriven_inputs_;
+  e_undriven_input_type constant_undriven_inputs_;
+  std::array<const char*, FabricVerilogOption::e_undriven_input_type::NUM_TYPES> CONSTANT_UNDRIVEN_INPUT_TYPE_STRING_; //String versions of constant undriven input types
   bool verbose_output_;
 };
 
diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp
index 4da841564..37b1bb526 100644
--- a/openfpga/src/fpga_verilog/verilog_grid.cpp
+++ b/openfpga/src/fpga_verilog/verilog_grid.cpp
@@ -113,9 +113,9 @@ static void print_verilog_primitive_block(
            module_manager.module_name(primitive_module).c_str());
 
   /* Write the verilog module */
-  write_verilog_module_to_file(fp, module_manager, primitive_module, true,
-                               options.constant_undriven_inputs(),
-                               options.default_net_type());
+  FabricVerilogOption curr_options = options;
+  curr_options.set_explicit_port_mapping(true);
+  write_verilog_module_to_file(fp, module_manager, primitive_module, curr_options);
 
   /* Close file handler */
   fp.close();
@@ -234,8 +234,7 @@ static void rec_print_verilog_logical_tile(
 
   /* Write the verilog module */
   write_verilog_module_to_file(
-    fp, module_manager, pb_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+    fp, module_manager, pb_module, options);
 
   print_verilog_comment(
     fp,
@@ -348,8 +347,7 @@ static void print_verilog_physical_tile_netlist(
     fp, std::string("----- BEGIN Grid Verilog module: " +
                     module_manager.module_name(grid_module) + " -----"));
   write_verilog_module_to_file(
-    fp, module_manager, grid_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+    fp, module_manager, grid_module, options);
 
   print_verilog_comment(
     fp, std::string("----- END Grid Verilog module: " +
diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp
index 45dc0b862..fb5a143a1 100644
--- a/openfpga/src/fpga_verilog/verilog_lut.cpp
+++ b/openfpga/src/fpga_verilog/verilog_lut.cpp
@@ -59,11 +59,12 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
     ModuleId lut_module = module_manager.find_module(
       module_name_map.name(circuit_lib.model_name(lut_model)));
     VTR_ASSERT(true == module_manager.valid_module_id(lut_module));
-    write_verilog_module_to_file(
-      fp, module_manager, lut_module,
+    FabricVerilogOption curr_options = options;
+    curr_options.set_explicit_port_mapping(
       options.explicit_port_mapping() ||
-        circuit_lib.dump_explicit_port_map(lut_model),
-      options.constant_undriven_inputs(), options.default_net_type());
+        circuit_lib.dump_explicit_port_map(lut_model));
+    write_verilog_module_to_file(
+      fp, module_manager, lut_module, curr_options);
   }
 
   /* Close the file handler */
diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp
index 99557e6b9..39ed7ea83 100644
--- a/openfpga/src/fpga_verilog/verilog_memory.cpp
+++ b/openfpga/src/fpga_verilog/verilog_memory.cpp
@@ -57,11 +57,12 @@ static void print_verilog_mux_memory_module(
       ModuleId mem_module = module_manager.find_module(module_name);
       VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
       /* Write the module content in Verilog format */
-      write_verilog_module_to_file(
-        fp, module_manager, mem_module,
+      FabricVerilogOption curr_options = options;
+      curr_options.set_explicit_port_mapping(
         options.explicit_port_mapping() ||
-          circuit_lib.dump_explicit_port_map(mux_model),
-        options.constant_undriven_inputs(), options.default_net_type());
+          circuit_lib.dump_explicit_port_map(mux_model));
+      write_verilog_module_to_file(
+        fp, module_manager, mem_module, curr_options);
 
       /* Add an empty line as a splitter */
       fp << std::endl;
@@ -81,10 +82,7 @@ static void print_verilog_mux_memory_module(
         VTR_ASSERT(true == module_manager.valid_module_id(feedthru_mem_module));
         /* Write the module content in Verilog format */
         write_verilog_module_to_file(
-          fp, module_manager, feedthru_mem_module,
-          options.explicit_port_mapping() ||
-            circuit_lib.dump_explicit_port_map(mux_model),
-          options.constant_undriven_inputs(), options.default_net_type());
+          fp, module_manager, feedthru_mem_module, curr_options);
 
         /* Add an empty line as a splitter */
         fp << std::endl;
@@ -205,11 +203,11 @@ void print_verilog_submodule_memories(
     ModuleId mem_module = module_manager.find_module(module_name);
     VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
     /* Write the module content in Verilog format */
-    write_verilog_module_to_file(fp, module_manager, mem_module,
-                                 options.explicit_port_mapping() ||
-                                   circuit_lib.dump_explicit_port_map(model),
-                                 options.constant_undriven_inputs(),
-                                 options.default_net_type());
+    FabricVerilogOption curr_options = options;
+    curr_options.set_explicit_port_mapping(
+      options.explicit_port_mapping() ||
+        circuit_lib.dump_explicit_port_map(model));
+    write_verilog_module_to_file(fp, module_manager, mem_module, curr_options);
 
     /* Add an empty line as a splitter */
     fp << std::endl;
@@ -227,10 +225,7 @@ void print_verilog_submodule_memories(
     if (module_manager.valid_module_id(feedthru_mem_module)) {
       /* Write the module content in Verilog format */
       write_verilog_module_to_file(fp, module_manager, feedthru_mem_module,
-                                   options.explicit_port_mapping() ||
-                                     circuit_lib.dump_explicit_port_map(model),
-                                   options.constant_undriven_inputs(),
-                                   options.default_net_type());
+                                   curr_options);
 
       /* Add an empty line as a splitter */
       fp << std::endl;
@@ -242,8 +237,7 @@ void print_verilog_submodule_memories(
          ModuleManager::e_module_usage_type::MODULE_CONFIG_GROUP)) {
     /* Write the module content in Verilog format */
     write_verilog_module_to_file(
-      fp, module_manager, mem_group_module, options.explicit_port_mapping(),
-      options.constant_undriven_inputs(), options.default_net_type());
+      fp, module_manager, mem_group_module, options);
 
     /* Add an empty line as a splitter */
     fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
index c99a088c0..3ed9bce57 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp
@@ -572,9 +572,8 @@ static void write_verilog_instance_to_file(std::fstream& fp,
  *******************************************************************/
 void write_verilog_module_to_file(
   std::fstream& fp, const ModuleManager& module_manager,
-  const ModuleId& module_id, const bool& use_explicit_port_map,
-  const bool& constant_local_undriven_wires,
-  const e_verilog_default_net_type& default_net_type) {
+  const ModuleId& module_id,
+  const FabricVerilogOption& options) {
   VTR_ASSERT(true == valid_file_stream(fp));
 
   /* Ensure we have a valid module_id */
@@ -582,7 +581,7 @@ void write_verilog_module_to_file(
 
   /* Print module declaration */
   print_verilog_module_declaration(fp, module_manager, module_id,
-                                   default_net_type);
+                                   options.default_net_type());
 
   /* Print an empty line as splitter */
   fp << std::endl;
@@ -595,7 +594,7 @@ void write_verilog_module_to_file(
     for (const BasicPort& local_wire : port_group.second) {
       /* When default net type is wire, we can skip single-bit wires whose LSB
        * is 0 */
-      if ((VERILOG_DEFAULT_NET_TYPE_WIRE == default_net_type) &&
+      if ((VERILOG_DEFAULT_NET_TYPE_WIRE == options.default_net_type()) &&
           (1 == local_wire.get_width()) && (0 == local_wire.get_lsb())) {
         continue;
       }
@@ -605,7 +604,7 @@ void write_verilog_module_to_file(
   }
 
   /* Use constant to drive undriven local wires */
-  if (constant_local_undriven_wires) {
+  if (options.constant_local_undriven_inputs() != FabricVerilogOption::e_undriven_input_type::NONE) {
     std::vector<ModuleManager::e_module_port_type> blacklist = {
       ModuleManager::e_module_port_type::MODULE_GLOBAL_PORT,
       ModuleManager::e_module_port_type::MODULE_GPIN_PORT,
@@ -620,9 +619,15 @@ void write_verilog_module_to_file(
     for (std::pair<std::string, std::vector<BasicPort>> port_group :
          local_undriven_wires) {
       for (const BasicPort& local_undriven_wire : port_group.second) {
-        print_verilog_wire_constant_values(
-          fp, local_undriven_wire,
-          std::vector<size_t>(local_undriven_wire.get_width(), 0));
+        if (options.constant_local_undriven_inputs_use_bus()) {
+          print_verilog_wire_constant_values(
+            fp, local_undriven_wire,
+            std::vector<size_t>(local_undriven_wire.get_width(), options.constant_local_undriven_inputs_value()));
+        } else {
+          print_verilog_wire_constant_values_bit_blast(
+            fp, local_undriven_wire,
+            std::vector<size_t>(local_undriven_wire.get_width(), options.constant_local_undriven_inputs_value()));
+        }
       }
     }
   }
@@ -653,7 +658,7 @@ void write_verilog_module_to_file(
       /* Print an instance */
       write_verilog_instance_to_file(fp, module_manager, module_id,
                                      child_module, instance,
-                                     use_explicit_port_map);
+                                     options.use_explicit_port_map());
       /* Print an empty line as splitter */
       fp << std::endl;
     }
@@ -661,7 +666,7 @@ void write_verilog_module_to_file(
 
   /* Print an end for the module */
   print_verilog_module_end(fp, module_manager.module_name(module_id),
-                           default_net_type);
+                           options.default_net_type());
 
   /* Print an empty line as splitter */
   fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.h b/openfpga/src/fpga_verilog/verilog_module_writer.h
index 0657c3985..c24b05d1c 100644
--- a/openfpga/src/fpga_verilog/verilog_module_writer.h
+++ b/openfpga/src/fpga_verilog/verilog_module_writer.h
@@ -8,6 +8,7 @@
 
 #include "module_manager.h"
 #include "verilog_port_types.h"
+#include "fabric_verilog_options.h"
 
 /********************************************************************
  * Function declaration
@@ -18,9 +19,8 @@ namespace openfpga {
 
 void write_verilog_module_to_file(
   std::fstream& fp, const ModuleManager& module_manager,
-  const ModuleId& module_id, const bool& use_explicit_port_map,
-  const bool& constant_local_undriven_wires,
-  const e_verilog_default_net_type& default_net_type);
+  const ModuleId& module_id, 
+  const FabricVerilogOption& options);
 
 } /* end namespace openfpga */
 
diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp
index 6f7a2a282..d6b323e62 100644
--- a/openfpga/src/fpga_verilog/verilog_mux.cpp
+++ b/openfpga/src/fpga_verilog/verilog_mux.cpp
@@ -643,8 +643,7 @@ static void generate_verilog_rram_mux_branch_module(
 static void generate_verilog_mux_branch_module(
   ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
   std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph,
-  const ModuleNameMap& module_name_map, const bool& use_explicit_port_map,
-  const e_verilog_default_net_type& default_net_type,
+  const ModuleNameMap& module_name_map, const FabricVerilogOption& options,
   std::map<std::string, bool>& branch_mux_module_is_outputted) {
   std::string module_name = generate_mux_branch_subckt_name(
     circuit_lib, mux_model, mux_graph.num_inputs(), mux_graph.num_memory_bits(),
@@ -675,11 +674,14 @@ static void generate_verilog_mux_branch_module(
         /* Structural verilog can be easily generated by module writer */
         ModuleId mux_module = module_manager.find_module(module_name);
         VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
+        FabricVerilogOption curr_options = options;
+        curr_options.set_explicit_port_mapping(
+          use_explicit_port_map ||
+            circuit_lib.dump_explicit_port_map(mux_model));
+        curr_options.set_constant_undriven_inputs(FabricVerilogOption::e_undriven_input_type::NONE);
         write_verilog_module_to_file(
           fp, module_manager, mux_module,
-          use_explicit_port_map ||
-            circuit_lib.dump_explicit_port_map(mux_model),
-          false, default_net_type);
+          curr_options);
         /* Add an empty line as a splitter */
         fp << std::endl;
       } else {
@@ -1417,13 +1419,17 @@ static void generate_verilog_mux_module(
       /* Use Verilog writer to print the module to file */
       ModuleId mux_module = module_manager.find_module(module_name);
       VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
-      write_verilog_module_to_file(
-        fp, module_manager, mux_module,
+      FabricVerilogOption curr_options = options;
+      curr_option.set_explict_port_mapping(
         (use_explicit_port_map ||
          circuit_lib.dump_explicit_port_map(mux_model) ||
          circuit_lib.dump_explicit_port_map(
-           circuit_lib.pass_gate_logic_model(mux_model))),
-        false, default_net_type);
+           circuit_lib.pass_gate_logic_model(mux_model)))
+      );
+      curr_option.set_constant_undriven_inputs(FabricVerilogOption::e_undriven_input_type::NONE);
+      write_verilog_module_to_file(
+        fp, module_manager, mux_module,
+        curr_options);
       /* Add an empty line as a splitter */
       fp << std::endl;
       break;
@@ -1486,8 +1492,7 @@ static void print_verilog_submodule_mux_primitives(
     for (auto branch_mux_graph : branch_mux_graphs) {
       generate_verilog_mux_branch_module(
         module_manager, circuit_lib, fp, mux_circuit_model, branch_mux_graph,
-        module_name_map, options.explicit_port_mapping(),
-        options.default_net_type(), branch_mux_module_is_outputted);
+        module_name_map, options, branch_mux_module_is_outputted);
     }
   }
 
diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp
index 00bcaeda5..aed1cacf8 100644
--- a/openfpga/src/fpga_verilog/verilog_routing.cpp
+++ b/openfpga/src/fpga_verilog/verilog_routing.cpp
@@ -116,8 +116,7 @@ static void print_verilog_routing_connection_box_unique_module(
 
   /* Write the verilog module */
   write_verilog_module_to_file(
-    fp, module_manager, cb_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+    fp, module_manager, cb_module, options);
 
   /* Add an empty line as a splitter */
   fp << std::endl;
@@ -237,8 +236,7 @@ static void print_verilog_routing_switch_box_unique_module(
 
   /* Write the verilog module */
   write_verilog_module_to_file(
-    fp, module_manager, sb_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+    fp, module_manager, sb_module, options);
 
   /* Close file handler */
   fp.close();
diff --git a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
index 6f548d8ec..2ce5687c3 100644
--- a/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
+++ b/openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
@@ -57,8 +57,7 @@ void print_verilog_submodule_shift_register_banks(
     VTR_ASSERT(true == module_manager.valid_module_id(sr_module));
     /* Write the module content in Verilog format */
     write_verilog_module_to_file(
-      fp, module_manager, sr_module, options.explicit_port_mapping(),
-      options.constant_undriven_inputs(), options.default_net_type());
+      fp, module_manager, sr_module, options);
 
     /* Add an empty line as a splitter */
     fp << std::endl;
@@ -68,8 +67,7 @@ void print_verilog_submodule_shift_register_banks(
     VTR_ASSERT(true == module_manager.valid_module_id(sr_module));
     /* Write the module content in Verilog format */
     write_verilog_module_to_file(
-      fp, module_manager, sr_module, options.explicit_port_mapping(),
-      options.constant_undriven_inputs(), options.default_net_type());
+      fp, module_manager, sr_module, options);
 
     /* Add an empty line as a splitter */
     fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_tile.cpp b/openfpga/src/fpga_verilog/verilog_tile.cpp
index a3bb1e992..85ba9385a 100644
--- a/openfpga/src/fpga_verilog/verilog_tile.cpp
+++ b/openfpga/src/fpga_verilog/verilog_tile.cpp
@@ -59,8 +59,7 @@ static int print_verilog_tile_module_netlist(
 
   /* Write the module content in Verilog format */
   write_verilog_module_to_file(
-    fp, module_manager, tile_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+    fp, module_manager, tile_module, options);
 
   /* Add an empty line as a splitter */
   fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp
index 26268e4c1..f7eb7db5f 100644
--- a/openfpga/src/fpga_verilog/verilog_top_module.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp
@@ -62,8 +62,7 @@ void print_verilog_core_module(NetlistManager& netlist_manager,
 
   /* Write the module content in Verilog format */
   write_verilog_module_to_file(
-    fp, module_manager, core_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+    fp, module_manager, core_module, options);
 
   /* Add an empty line as a splitter */
   fp << std::endl;
@@ -128,8 +127,7 @@ void print_verilog_top_module(NetlistManager& netlist_manager,
 
   /* Write the module content in Verilog format */
   write_verilog_module_to_file(
-    fp, module_manager, top_module, options.explicit_port_mapping(),
-    options.constant_undriven_inputs(), options.default_net_type());
+    fp, module_manager, top_module, options);
 
   /* Add an empty line as a splitter */
   fp << std::endl;
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
index dd95205de..8169b80ff 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp
@@ -831,6 +831,22 @@ void print_verilog_wire_constant_values(
   fp << ";" << std::endl;
 }
 
+/********************************************************************
+ * Generate a wire connection, that assigns constant values to a
+ * Verilog port
+ *******************************************************************/
+void print_verilog_wire_constant_values_bit_blast(
+  std::fstream& fp, const BasicPort& output_port,
+  const std::vector<size_t>& const_values) {
+  /* Make sure we have a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  for (size_t ipin : output_port.pins()) {
+    BasicPort curr_pin(output_port.get_name(), ipin, ipin);
+    print_verilog_wire_constant_values_bit_blast(fp, curr_pin, const_values[ipin]);
+  }
+}
+
 /********************************************************************
  * Deposit constant values to a Verilog port
  *******************************************************************/
diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.h b/openfpga/src/fpga_verilog/verilog_writer_utils.h
index 665f191a2..cffd10425 100644
--- a/openfpga/src/fpga_verilog/verilog_writer_utils.h
+++ b/openfpga/src/fpga_verilog/verilog_writer_utils.h
@@ -123,6 +123,10 @@ void print_verilog_wire_constant_values(
   std::fstream& fp, const BasicPort& output_port,
   const std::vector<size_t>& const_values);
 
+void print_verilog_wire_constant_values_bit_blast(
+  std::fstream& fp, const BasicPort& output_port,
+  const std::vector<size_t>& const_values);
+
 void print_verilog_deposit_wire_constant_values(
   std::fstream& fp, const BasicPort& output_port,
   const std::vector<size_t>& const_values);