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[core] code format

This commit is contained in:
tangxifan 2024-06-26 22:47:29 -07:00
parent 5d0b0b9a8c
commit ac1ad52795
5 changed files with 42 additions and 43 deletions
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18
openfpga/src/annotation/openfpga_annotate_routing.cpp
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@ -19,10 +19,9 @@ namespace openfpga {
* - Note that this function is different than annotate_vpr_rr_nodes() * - Note that this function is different than annotate_vpr_rr_nodes()
* Please do not annotate global nets in vpr_routing_annotation! * Please do not annotate global nets in vpr_routing_annotation!
*******************************************************************/ *******************************************************************/
vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(const DeviceContext& device_ctx, vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(
const ClusteredNetlist& cluster_nlist, const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist,
const PlacementContext& placement_ctx, const PlacementContext& placement_ctx, const bool& verbose) {
const bool& verbose) {
vtr::vector<RRNodeId, ClusterNetId> rr_node_nets; vtr::vector<RRNodeId, ClusterNetId> rr_node_nets;
size_t counter = 0; size_t counter = 0;
@ -31,7 +30,7 @@ vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(const DeviceCont
const auto& rr_graph = device_ctx.rr_graph; const auto& rr_graph = device_ctx.rr_graph;
rr_node_nets.resize(rr_graph.num_nodes(), ClusterNetId::INVALID()); rr_node_nets.resize(rr_graph.num_nodes(), ClusterNetId::INVALID());
size_t layer = 0; size_t layer = 0;
for (ClusterNetId net_id : cluster_nlist.nets()) { for (ClusterNetId net_id : cluster_nlist.nets()) {
@ -39,11 +38,13 @@ vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(const DeviceCont
continue; continue;
} }
/* Walk through all the sinks */ /* Walk through all the sinks */
for (ClusterPinId pin_id : cluster_nlist.net_pins(net_id)) { for (ClusterPinId pin_id : cluster_nlist.net_pins(net_id)) {
ClusterBlockId block_id = cluster_nlist.pin_block(pin_id); ClusterBlockId block_id = cluster_nlist.pin_block(pin_id);
t_block_loc blk_loc = get_block_loc(block_id, false); t_block_loc blk_loc = get_block_loc(block_id, false);
int phy_pin = placement_ctx.physical_pins[pin_id]; int phy_pin = placement_ctx.physical_pins[pin_id];
std::vector<RRNodeId> curr_rr_nodes = rr_graph.node_lookup().find_nodes_at_all_sides(layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, phy_pin); std::vector<RRNodeId> curr_rr_nodes =
rr_graph.node_lookup().find_nodes_at_all_sides(
layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, phy_pin);
for (RRNodeId curr_rr_node : curr_rr_nodes) { for (RRNodeId curr_rr_node : curr_rr_nodes) {
rr_node_nets[curr_rr_node] = net_id; rr_node_nets[curr_rr_node] = net_id;
} }
@ -52,7 +53,6 @@ vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(const DeviceCont
VTR_LOGV(verbose, "Done with %d nodes mapping\n", counter); VTR_LOGV(verbose, "Done with %d nodes mapping\n", counter);
return rr_node_nets; return rr_node_nets;
} }

8
openfpga/src/annotation/openfpga_annotate_routing.h
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@ -15,11 +15,9 @@
/* begin namespace openfpga */ /* begin namespace openfpga */
namespace openfpga { namespace openfpga {
vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(const DeviceContext& device_ctx, vtr::vector<RRNodeId, ClusterNetId> annotate_rr_node_global_net(
const ClusteredNetlist& cluster_nlist, const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist,
const PlacementContext& placement_ctx, const PlacementContext& placement_ctx, const bool& verbose);
const bool& verbose);
void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx, void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx,
const ClusteringContext& clustering_ctx, const ClusteringContext& clustering_ctx,

39
openfpga/src/annotation/route_clock_rr_graph.cpp
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@ -1,12 +1,12 @@
#include "route_clock_rr_graph.h" #include "route_clock_rr_graph.h"
#include "command_exit_codes.h" #include "command_exit_codes.h"
#include "openfpga_annotate_routing.h"
#include "openfpga_atom_netlist_utils.h" #include "openfpga_atom_netlist_utils.h"
#include "vtr_assert.h" #include "vtr_assert.h"
#include "vtr_geometry.h" #include "vtr_geometry.h"
#include "vtr_log.h" #include "vtr_log.h"
#include "vtr_time.h" #include "vtr_time.h"
#include "openfpga_annotate_routing.h"
/* begin namespace openfpga */ /* begin namespace openfpga */
namespace openfpga { namespace openfpga {
@ -177,17 +177,23 @@ static int route_clock_tree_rr_graph(
/* if the IPIN is mapped, only connect when net mapping is /* if the IPIN is mapped, only connect when net mapping is
* expected */ * expected */
if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) {
VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the tree is not used\n", VTR_LOGV(verbose,
"Skip routing clock tap of spine '%s' as the tree is "
"not used\n",
clk_ntwk.spine_name(ispine).c_str()); clk_ntwk.spine_name(ispine).c_str());
continue; continue;
} }
if (!rr_node_gnets[des_node]) { if (!rr_node_gnets[des_node]) {
VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the IPIN is not mapped\n", VTR_LOGV(verbose,
"Skip routing clock tap of spine '%s' as the IPIN is "
"not mapped\n",
clk_ntwk.spine_name(ispine).c_str()); clk_ntwk.spine_name(ispine).c_str());
continue; continue;
} }
if (rr_node_gnets[des_node] != tree2clk_pin_map.at(ipin)) { if (rr_node_gnets[des_node] != tree2clk_pin_map.at(ipin)) {
VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the net mapping does not match clock net\n", VTR_LOGV(verbose,
"Skip routing clock tap of spine '%s' as the net "
"mapping does not match clock net\n",
clk_ntwk.spine_name(ispine).c_str()); clk_ntwk.spine_name(ispine).c_str());
continue; continue;
} }
@ -216,16 +222,13 @@ static int route_clock_tree_rr_graph(
* - configure the routing annotation w.r.t. the clock node connections * - configure the routing annotation w.r.t. the clock node connections
* - quick check to ensure routing is valid * - quick check to ensure routing is valid
*******************************************************************/ *******************************************************************/
int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, int route_clock_rr_graph(
const DeviceContext& vpr_device_ctx, VprRoutingAnnotation& vpr_routing_annotation,
const AtomContext& atom_ctx, const DeviceContext& vpr_device_ctx, const AtomContext& atom_ctx,
const ClusteredNetlist& cluster_nlist, const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx,
const PlacementContext& vpr_place_ctx, const VprNetlistAnnotation& netlist_annotation,
const VprNetlistAnnotation& netlist_annotation, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& clk_rr_lookup, const PinConstraints& pin_constraints, const bool& verbose) {
const ClockNetwork& clk_ntwk,
const PinConstraints& pin_constraints,
const bool& verbose) {
vtr::ScopedStartFinishTimer timer( vtr::ScopedStartFinishTimer timer(
"Route programmable clock network based on routing resource graph"); "Route programmable clock network based on routing resource graph");
@ -256,7 +259,9 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation,
} }
/* Build rr_node-to-net mapping for global nets */ /* Build rr_node-to-net mapping for global nets */
vtr::vector<RRNodeId, ClusterNetId> rr_node_gnets = annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx, verbose); vtr::vector<RRNodeId, ClusterNetId> rr_node_gnets =
annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx,
verbose);
/* Route spines one by one */ /* Route spines one by one */
for (auto itree : clk_ntwk.trees()) { for (auto itree : clk_ntwk.trees()) {
@ -274,8 +279,8 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation,
VTR_LOGV(verbose, "Routing clock tree '%s'...\n", VTR_LOGV(verbose, "Routing clock tree '%s'...\n",
clk_ntwk.tree_name(itree).c_str()); clk_ntwk.tree_name(itree).c_str());
status = route_clock_tree_rr_graph( status = route_clock_tree_rr_graph(
vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup, rr_node_gnets, vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup,
tree2clk_pin_map, clk_ntwk, itree, verbose); rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree, verbose);
if (status == CMD_EXEC_FATAL_ERROR) { if (status == CMD_EXEC_FATAL_ERROR) {
return status; return status;
} }

17
openfpga/src/annotation/route_clock_rr_graph.h
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@ -18,16 +18,13 @@
/* begin namespace openfpga */ /* begin namespace openfpga */
namespace openfpga { namespace openfpga {
int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, int route_clock_rr_graph(
const DeviceContext& vpr_device_ctx, VprRoutingAnnotation& vpr_routing_annotation,
const AtomContext& atom_ctx, const DeviceContext& vpr_device_ctx, const AtomContext& atom_ctx,
const ClusteredNetlist& cluster_nlist, const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx,
const PlacementContext& vpr_place_ctx, const VprNetlistAnnotation& netlist_annotation,
const VprNetlistAnnotation& netlist_annotation, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& clk_rr_lookup, const PinConstraints& pin_constraints, const bool& verbose);
const ClockNetwork& clk_ntwk,
const PinConstraints& pin_constraints,
const bool& verbose);
} /* end namespace openfpga */ } /* end namespace openfpga */

3
openfpga/src/base/openfpga_link_arch_template.h
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@ -230,8 +230,7 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd,
return route_clock_rr_graph( return route_clock_rr_graph(
openfpga_ctx.mutable_vpr_routing_annotation(), g_vpr_ctx.device(), openfpga_ctx.mutable_vpr_routing_annotation(), g_vpr_ctx.device(),
g_vpr_ctx.atom(), g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.atom(), g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(),
g_vpr_ctx.placement(),
openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.clock_rr_lookup(), openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.clock_rr_lookup(),
openfpga_ctx.clock_arch(), pin_constraints, openfpga_ctx.clock_arch(), pin_constraints,
cmd_context.option_enable(cmd, opt_verbose)); cmd_context.option_enable(cmd, opt_verbose));