From ac1ad527951b8e7dee1e05869812dbe160245152 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 26 Jun 2024 22:47:29 -0700 Subject: [PATCH] [core] code format --- .../annotation/openfpga_annotate_routing.cpp | 18 ++++----- .../annotation/openfpga_annotate_routing.h | 8 ++-- .../src/annotation/route_clock_rr_graph.cpp | 39 +++++++++++-------- .../src/annotation/route_clock_rr_graph.h | 17 ++++---- .../src/base/openfpga_link_arch_template.h | 3 +- 5 files changed, 42 insertions(+), 43 deletions(-) diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index 8c19cd2c7..ad84d86e2 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -19,10 +19,9 @@ namespace openfpga { * - Note that this function is different than annotate_vpr_rr_nodes() * Please do not annotate global nets in vpr_routing_annotation! *******************************************************************/ -vtr::vector annotate_rr_node_global_net(const DeviceContext& device_ctx, - const ClusteredNetlist& cluster_nlist, - const PlacementContext& placement_ctx, - const bool& verbose) { +vtr::vector annotate_rr_node_global_net( + const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& placement_ctx, const bool& verbose) { vtr::vector rr_node_nets; size_t counter = 0; @@ -31,7 +30,7 @@ vtr::vector annotate_rr_node_global_net(const DeviceCont const auto& rr_graph = device_ctx.rr_graph; rr_node_nets.resize(rr_graph.num_nodes(), ClusterNetId::INVALID()); - + size_t layer = 0; for (ClusterNetId net_id : cluster_nlist.nets()) { @@ -39,11 +38,13 @@ vtr::vector annotate_rr_node_global_net(const DeviceCont continue; } /* Walk through all the sinks */ - for (ClusterPinId pin_id : cluster_nlist.net_pins(net_id)) { + for (ClusterPinId pin_id : cluster_nlist.net_pins(net_id)) { ClusterBlockId block_id = cluster_nlist.pin_block(pin_id); - t_block_loc blk_loc = get_block_loc(block_id, false); + t_block_loc blk_loc = get_block_loc(block_id, false); int phy_pin = placement_ctx.physical_pins[pin_id]; - std::vector curr_rr_nodes = rr_graph.node_lookup().find_nodes_at_all_sides(layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, phy_pin); + std::vector curr_rr_nodes = + rr_graph.node_lookup().find_nodes_at_all_sides( + layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, phy_pin); for (RRNodeId curr_rr_node : curr_rr_nodes) { rr_node_nets[curr_rr_node] = net_id; } @@ -52,7 +53,6 @@ vtr::vector annotate_rr_node_global_net(const DeviceCont VTR_LOGV(verbose, "Done with %d nodes mapping\n", counter); - return rr_node_nets; } diff --git a/openfpga/src/annotation/openfpga_annotate_routing.h b/openfpga/src/annotation/openfpga_annotate_routing.h index 2578e86bd..dc5d28db3 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.h +++ b/openfpga/src/annotation/openfpga_annotate_routing.h @@ -15,11 +15,9 @@ /* begin namespace openfpga */ namespace openfpga { -vtr::vector annotate_rr_node_global_net(const DeviceContext& device_ctx, - const ClusteredNetlist& cluster_nlist, - const PlacementContext& placement_ctx, - const bool& verbose); - +vtr::vector annotate_rr_node_global_net( + const DeviceContext& device_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& placement_ctx, const bool& verbose); void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 77de0175b..327a51f40 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -1,12 +1,12 @@ #include "route_clock_rr_graph.h" #include "command_exit_codes.h" +#include "openfpga_annotate_routing.h" #include "openfpga_atom_netlist_utils.h" #include "vtr_assert.h" #include "vtr_geometry.h" #include "vtr_log.h" #include "vtr_time.h" -#include "openfpga_annotate_routing.h" /* begin namespace openfpga */ namespace openfpga { @@ -177,17 +177,23 @@ static int route_clock_tree_rr_graph( /* if the IPIN is mapped, only connect when net mapping is * expected */ if (tree2clk_pin_map.find(ipin) == tree2clk_pin_map.end()) { - VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the tree is not used\n", + VTR_LOGV(verbose, + "Skip routing clock tap of spine '%s' as the tree is " + "not used\n", clk_ntwk.spine_name(ispine).c_str()); continue; } if (!rr_node_gnets[des_node]) { - VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the IPIN is not mapped\n", + VTR_LOGV(verbose, + "Skip routing clock tap of spine '%s' as the IPIN is " + "not mapped\n", clk_ntwk.spine_name(ispine).c_str()); continue; } if (rr_node_gnets[des_node] != tree2clk_pin_map.at(ipin)) { - VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the net mapping does not match clock net\n", + VTR_LOGV(verbose, + "Skip routing clock tap of spine '%s' as the net " + "mapping does not match clock net\n", clk_ntwk.spine_name(ispine).c_str()); continue; } @@ -216,16 +222,13 @@ static int route_clock_tree_rr_graph( * - configure the routing annotation w.r.t. the clock node connections * - quick check to ensure routing is valid *******************************************************************/ -int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, - const DeviceContext& vpr_device_ctx, - const AtomContext& atom_ctx, - const ClusteredNetlist& cluster_nlist, - const PlacementContext& vpr_place_ctx, - const VprNetlistAnnotation& netlist_annotation, - const RRClockSpatialLookup& clk_rr_lookup, - const ClockNetwork& clk_ntwk, - const PinConstraints& pin_constraints, - const bool& verbose) { +int route_clock_rr_graph( + VprRoutingAnnotation& vpr_routing_annotation, + const DeviceContext& vpr_device_ctx, const AtomContext& atom_ctx, + const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, + const VprNetlistAnnotation& netlist_annotation, + const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, + const PinConstraints& pin_constraints, const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Route programmable clock network based on routing resource graph"); @@ -256,7 +259,9 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, } /* Build rr_node-to-net mapping for global nets */ - vtr::vector rr_node_gnets = annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx, verbose); + vtr::vector rr_node_gnets = + annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx, + verbose); /* Route spines one by one */ for (auto itree : clk_ntwk.trees()) { @@ -274,8 +279,8 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, VTR_LOGV(verbose, "Routing clock tree '%s'...\n", clk_ntwk.tree_name(itree).c_str()); status = route_clock_tree_rr_graph( - vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup, rr_node_gnets, - tree2clk_pin_map, clk_ntwk, itree, verbose); + vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup, + rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree, verbose); if (status == CMD_EXEC_FATAL_ERROR) { return status; } diff --git a/openfpga/src/annotation/route_clock_rr_graph.h b/openfpga/src/annotation/route_clock_rr_graph.h index e12767e9b..f0d60642c 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.h +++ b/openfpga/src/annotation/route_clock_rr_graph.h @@ -18,16 +18,13 @@ /* begin namespace openfpga */ namespace openfpga { -int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, - const DeviceContext& vpr_device_ctx, - const AtomContext& atom_ctx, - const ClusteredNetlist& cluster_nlist, - const PlacementContext& vpr_place_ctx, - const VprNetlistAnnotation& netlist_annotation, - const RRClockSpatialLookup& clk_rr_lookup, - const ClockNetwork& clk_ntwk, - const PinConstraints& pin_constraints, - const bool& verbose); +int route_clock_rr_graph( + VprRoutingAnnotation& vpr_routing_annotation, + const DeviceContext& vpr_device_ctx, const AtomContext& atom_ctx, + const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, + const VprNetlistAnnotation& netlist_annotation, + const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, + const PinConstraints& pin_constraints, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index 319c89086..2e742742a 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -230,8 +230,7 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, return route_clock_rr_graph( openfpga_ctx.mutable_vpr_routing_annotation(), g_vpr_ctx.device(), - g_vpr_ctx.atom(), g_vpr_ctx.clustering().clb_nlist, - g_vpr_ctx.placement(), + g_vpr_ctx.atom(), g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(), openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints, cmd_context.option_enable(cmd, opt_verbose));