riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #839 from yunuseryilmaz18/patch-2 

Update frac_mem_32k.v
This commit is contained in:
tangxifan 2022-10-12 17:59:58 -07:00 committed by GitHub
parent d79ada8720 f62d435b1e
commit a9e45be8cc
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 7 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
openfpga_flow/openfpga_cell_library/verilog/frac_mem_32k.v
View File

@ -161,11 +161,15 @@ module frac_mem_32k (
end else if (4'b0111 == mode) begin end else if (4'b0111 == mode) begin
if (we_a) begin if (we_a) begin
ram_a[addr_a[0:9]] <= data_a; ram_a[addr_a[0:9]] <= data_a;
ram_b[addr_b[0:9]] <= data_b;
q_a <= data_a; q_a <= data_a;
q_b <= data_b;
end else begin end else begin
q_a <= ram_a[addr_a[0:9]]; q_a <= ram_a[addr_a[0:9]];
end
if (we_b) begin
ram_b[addr_b[0:9]] <= data_b;
q_b <= data_b;
end else begin
q_b <= ram_b[addr_b[0:9]]; q_b <= ram_b[addr_b[0:9]];
end end
// Operating mode: dual port RAM 2048 x 16 // Operating mode: dual port RAM 2048 x 16