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remame methods in circuit_library

This commit is contained in:
tangxifan 2019-08-19 20:43:35 -06:00
parent 69039aa742
commit a7ac1e4980
10 changed files with 998 additions and 991 deletions
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48
vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp
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@ -58,16 +58,16 @@ static
size_t check_circuit_library_unique_names(const CircuitLibrary& circuit_lib) { size_t check_circuit_library_unique_names(const CircuitLibrary& circuit_lib) {
size_t num_err = 0; size_t num_err = 0;
for (size_t i = 0; i < circuit_lib.num_circuit_models(); ++i) { for (size_t i = 0; i < circuit_lib.num_models(); ++i) {
/* Skip for the last element, because the inner loop will access it */ /* Skip for the last element, because the inner loop will access it */
if (i == circuit_lib.num_circuit_models() - 1) { if (i == circuit_lib.num_models() - 1) {
continue; continue;
} }
/* Get the name of reference */ /* Get the name of reference */
const std::string& i_name = circuit_lib.circuit_model_name(CircuitModelId(i)); const std::string& i_name = circuit_lib.model_name(CircuitModelId(i));
for (size_t j = i + 1; j < circuit_lib.num_circuit_models(); ++j) { for (size_t j = i + 1; j < circuit_lib.num_models(); ++j) {
/* Compare the name of candidate */ /* Compare the name of candidate */
const std::string& j_name = circuit_lib.circuit_model_name(CircuitModelId(j)); const std::string& j_name = circuit_lib.model_name(CircuitModelId(j));
/* Compare the name and skip for different names */ /* Compare the name and skip for different names */
if (0 != i_name.compare(j_name)) { if (0 != i_name.compare(j_name)) {
continue; continue;
@ -92,24 +92,24 @@ static
size_t check_circuit_library_unique_prefix(const CircuitLibrary& circuit_lib) { size_t check_circuit_library_unique_prefix(const CircuitLibrary& circuit_lib) {
size_t num_err = 0; size_t num_err = 0;
for (size_t i = 0; i < circuit_lib.num_circuit_models(); ++i) { for (size_t i = 0; i < circuit_lib.num_models(); ++i) {
/* Skip for the last element, because the inner loop will access it */ /* Skip for the last element, because the inner loop will access it */
if (i == circuit_lib.num_circuit_models() - 1) { if (i == circuit_lib.num_models() - 1) {
continue; continue;
} }
/* Get the name of reference */ /* Get the name of reference */
const std::string& i_prefix = circuit_lib.circuit_model_prefix(CircuitModelId(i)); const std::string& i_prefix = circuit_lib.model_prefix(CircuitModelId(i));
for (size_t j = i + 1; j < circuit_lib.num_circuit_models(); ++j) { for (size_t j = i + 1; j < circuit_lib.num_models(); ++j) {
/* Compare the name of candidate */ /* Compare the name of candidate */
const std::string& j_prefix = circuit_lib.circuit_model_prefix(CircuitModelId(j)); const std::string& j_prefix = circuit_lib.model_prefix(CircuitModelId(j));
/* Compare the name and skip for different prefix */ /* Compare the name and skip for different prefix */
if (0 != i_prefix.compare(j_prefix)) { if (0 != i_prefix.compare(j_prefix)) {
continue; continue;
} }
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"Circuit model(name=%s) and (name=%s) share the same prefix, which is invalid!\n", "Circuit model(name=%s) and (name=%s) share the same prefix, which is invalid!\n",
circuit_lib.circuit_model_name(CircuitModelId(i)).c_str(), circuit_lib.model_name(CircuitModelId(i)).c_str(),
circuit_lib.circuit_model_name(CircuitModelId(j)).c_str(), circuit_lib.model_name(CircuitModelId(j)).c_str(),
i_prefix.c_str()); i_prefix.c_str());
/* Incremental the counter for errors */ /* Incremental the counter for errors */
num_err++; num_err++;
@ -129,7 +129,7 @@ size_t check_circuit_model_required(const CircuitLibrary& circuit_lib,
size_t num_err = 0; size_t num_err = 0;
/* We must have an IOPAD*/ /* We must have an IOPAD*/
if ( 0 == circuit_lib.circuit_models_by_type(circuit_model_type_to_check).size()) { if ( 0 == circuit_lib.models_by_type(circuit_model_type_to_check).size()) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"At least one %s circuit model is required!\n", "At least one %s circuit model is required!\n",
CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type_to_check)]); CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type_to_check)]);
@ -153,8 +153,8 @@ size_t check_one_circuit_model_port_required(const CircuitLibrary& circuit_lib,
if (0 == circuit_lib.ports_by_type(circuit_model, port_type).size()) { if (0 == circuit_lib.ports_by_type(circuit_model, port_type).size()) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"%s circuit model(name=%s) does not have %s port\n", "%s circuit model(name=%s) does not have %s port\n",
CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.circuit_model_type(circuit_model))], CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))],
circuit_lib.circuit_model_name(circuit_model).c_str(), circuit_lib.model_name(circuit_model).c_str(),
CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type)]); CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type)]);
/* Incremental the counter for errors */ /* Incremental the counter for errors */
num_err++; num_err++;
@ -178,7 +178,7 @@ size_t check_one_circuit_model_port_size_required(const CircuitLibrary& circuit_
if (port_size_to_check != circuit_lib.port_size(circuit_model, circuit_port)) { if (port_size_to_check != circuit_lib.port_size(circuit_model, circuit_port)) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"Port of circuit model(name=%s) does not have a port(type=%s) of size=%d.\n", "Port of circuit model(name=%s) does not have a port(type=%s) of size=%d.\n",
circuit_lib.circuit_model_name(circuit_model).c_str(), circuit_lib.model_name(circuit_model).c_str(),
CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(circuit_model, circuit_port))], CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(circuit_model, circuit_port))],
port_size_to_check); port_size_to_check);
/* Incremental the counter for errors */ /* Incremental the counter for errors */
@ -208,7 +208,7 @@ size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary&
"Expect %d %s ports for a %s circuit model, but only have %d %s ports!\n", "Expect %d %s ports for a %s circuit model, but only have %d %s ports!\n",
num_ports_to_check, num_ports_to_check,
CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)], CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)],
CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.circuit_model_type(circuit_model))], CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))],
CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)], CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)],
ports.size()); ports.size());
num_err++; num_err++;
@ -232,7 +232,7 @@ size_t check_circuit_model_port_required(const CircuitLibrary& circuit_lib,
const std::vector<enum e_spice_model_port_type>& port_types_to_check) { const std::vector<enum e_spice_model_port_type>& port_types_to_check) {
size_t num_err = 0; size_t num_err = 0;
for (const auto& id : circuit_lib.circuit_models_by_type(circuit_model_type_to_check)) { for (const auto& id : circuit_lib.models_by_type(circuit_model_type_to_check)) {
num_err += check_one_circuit_model_port_required(circuit_lib, id, port_types_to_check); num_err += check_one_circuit_model_port_required(circuit_lib, id, port_types_to_check);
} }
@ -248,7 +248,7 @@ size_t check_required_default_circuit_model(const CircuitLibrary& circuit_lib,
const enum e_spice_model_type& circuit_model_type) { const enum e_spice_model_type& circuit_model_type) {
size_t num_err = 0; size_t num_err = 0;
if (CIRCUIT_MODEL_OPEN_ID == circuit_lib.default_circuit_model(circuit_model_type)) { if (CircuitModelId::INVALID() == circuit_lib.default_model(circuit_model_type)) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"A default circuit model for the type %s! Try to define it in your architecture file!\n", "A default circuit model for the type %s! Try to define it in your architecture file!\n",
CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type)]); CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type)]);
@ -266,7 +266,7 @@ size_t check_ff_circuit_model_ports(const CircuitLibrary& circuit_lib,
size_t num_err = 0; size_t num_err = 0;
/* Check the type of circuit model */ /* Check the type of circuit model */
VTR_ASSERT(SPICE_MODEL_FF == circuit_lib.circuit_model_type(circuit_model)); VTR_ASSERT(SPICE_MODEL_FF == circuit_lib.model_type(circuit_model));
/* Check if we have D, Set and Reset */ /* Check if we have D, Set and Reset */
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
SPICE_MODEL_PORT_INPUT, SPICE_MODEL_PORT_INPUT,
@ -293,7 +293,7 @@ size_t check_scff_circuit_model_ports(const CircuitLibrary& circuit_lib,
size_t num_err = 0; size_t num_err = 0;
/* Check the type of circuit model */ /* Check the type of circuit model */
VTR_ASSERT(SPICE_MODEL_SCFF == circuit_lib.circuit_model_type(circuit_model)); VTR_ASSERT(SPICE_MODEL_SCFF == circuit_lib.model_type(circuit_model));
/* Check if we have D, Set and Reset */ /* Check if we have D, Set and Reset */
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
@ -322,7 +322,7 @@ size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib,
size_t num_err = 0; size_t num_err = 0;
/* Check the type of circuit model */ /* Check the type of circuit model */
VTR_ASSERT(SPICE_MODEL_SRAM == circuit_lib.circuit_model_type(circuit_model)); VTR_ASSERT(SPICE_MODEL_SRAM == circuit_lib.model_type(circuit_model));
/* Check if we has 1 output with size 2 */ /* Check if we has 1 output with size 2 */
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
@ -403,8 +403,8 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) {
num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_MUX, mux_port_types_required); num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_MUX, mux_port_types_required);
/* 5. We must have at least one SRAM or SCFF */ /* 5. We must have at least one SRAM or SCFF */
if ( ( 0 == circuit_lib.circuit_models_by_type(SPICE_MODEL_SRAM).size()) if ( ( 0 == circuit_lib.models_by_type(SPICE_MODEL_SRAM).size())
&& ( 0 == circuit_lib.circuit_models_by_type(SPICE_MODEL_SCFF).size()) ) { && ( 0 == circuit_lib.models_by_type(SPICE_MODEL_SCFF).size()) ) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"At least one %s or %s circuit model is required!\n", "At least one %s or %s circuit model is required!\n",
CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_SRAM)], CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_SRAM)],

4
vpr7_x2p/libarchfpga/SRC/check_circuit_library.h
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@ -47,7 +47,9 @@
*/ */
/* Header files should be included in a sequence */ /* Header files should be included in a sequence */
/* Standard header files required go first */ /* Standard header files required go first */
#include "circuit_library.h" #include <vector>
#include "spice_types.h"
#include "circuit_library_fwd.h"
/* Check points to make sure we have a valid circuit library */ /* Check points to make sure we have a valid circuit library */
size_t check_one_circuit_model_port_required(const CircuitLibrary& circuit_lib, size_t check_one_circuit_model_port_required(const CircuitLibrary& circuit_lib,

1432
vpr7_x2p/libarchfpga/SRC/circuit_library.cpp
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File diff suppressed because it is too large Load Diff

378
vpr7_x2p/libarchfpga/SRC/circuit_library.h
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@ -49,7 +49,6 @@
/* Standard header files required go first */ /* Standard header files required go first */
#include <string> #include <string>
#include "vtr_strong_id.h"
#include "vtr_geometry.h" #include "vtr_geometry.h"
#include "vtr_vector.h" #include "vtr_vector.h"
@ -57,22 +56,7 @@
#include "circuit_types.h" #include "circuit_types.h"
/************************************************************************ #include "circuit_library_fwd.h"
* Create strong id for Circuit Models/Ports to avoid illegal type casting
***********************************************************************/
struct circuit_model_id_tag;
struct circuit_port_id_tag;
struct circuit_edge_id_tag;
typedef vtr::StrongId<circuit_model_id_tag> CircuitModelId;
typedef vtr::StrongId<circuit_port_id_tag> CircuitPortId;
typedef vtr::StrongId<circuit_edge_id_tag> CircuitEdgeId;
/* Alias for open ids */
#define CIRCUIT_MODEL_OPEN_ID CircuitModelId(-1)
#define CIRCUIT_PORT_OPEN_ID CircuitPortId(-1)
#define CIRCUIT_EDGE_OPEN_ID CircuitEdgeId(-1)
/************************************************************************ /************************************************************************
* The class CircuitLibrary is a critical data structure for OpenFPGA * The class CircuitLibrary is a critical data structure for OpenFPGA
@ -81,20 +65,20 @@ typedef vtr::StrongId<circuit_edge_id_tag> CircuitEdgeId;
* It includes the following data: * It includes the following data:
* *
* ------ Fundamental Information ----- * ------ Fundamental Information -----
* 1. circuit_model_ids_ : unique identifier to find a circuit model * 1. model_ids_ : unique identifier to find a circuit model
* Use a strong id for search, to avoid illegal type casting * Use a strong id for search, to avoid illegal type casting
* 2. circuit_model_types_: types of the circuit model, see details in the definition of enum e_spice_model_type * 2. model_types_: types of the circuit model, see details in the definition of enum e_spice_model_type
* 3. circuit_model_names_: unique names for each circuit models. * 3. model_names_: unique names for each circuit models.
* It should be the same as user-defined Verilog modules, if it is not auto-generated * It should be the same as user-defined Verilog modules, if it is not auto-generated
* 4. circuit_model_prefix_: the prefix of a circuit model when it is instanciated * 4. model_prefix_: the prefix of a circuit model when it is instanciated
* 5. verilog_netlist_: specified path and file name of Verilog netlist if a circuit model is not auto-generated * 5. verilog_netlist_: specified path and file name of Verilog netlist if a circuit model is not auto-generated
* 6. spice_netlist_: specified path and file name of SPICE netlist if a circuit model is not auto-generated * 6. spice_netlist_: specified path and file name of SPICE netlist if a circuit model is not auto-generated
* 7. is_default_: indicate if the circuit model is the default one among all those in the same type * 7. is_default_: indicate if the circuit model is the default one among all those in the same type
* *
* ------ Fast look-ups----- * ------ Fast look-ups-----
* 1. circuit_model_lookup_: A multi-dimension vector to provide fast look-up on circuit models for users * 1. model_lookup_: A multi-dimension vector to provide fast look-up on circuit models for users
* It classifies CircuitModelIds by their type and set the default model in the first element for each type. * It classifies CircuitModelIds by their type and set the default model in the first element for each type.
* 2. circuit_model_port_lookup_: A multi-dimension vector to provide fast look-up on ports of circuit models for users * 2. model_port_lookup_: A multi-dimension vector to provide fast look-up on ports of circuit models for users
* It classifies Ports by their types * It classifies Ports by their types
* *
* ------ Verilog generation options ----- * ------ Verilog generation options -----
@ -109,12 +93,12 @@ typedef vtr::StrongId<circuit_edge_id_tag> CircuitEdgeId;
* Use vectors to simplify the defition of buffer existence: * Use vectors to simplify the defition of buffer existence:
* index (low=0 to high) represents INPUT, OUTPUT, LUT_INPUT_BUF, LUT_INPUT_INV, LUT_INTER_BUFFER * index (low=0 to high) represents INPUT, OUTPUT, LUT_INPUT_BUF, LUT_INPUT_INV, LUT_INTER_BUFFER
* 1. buffer_existence_: specify if this circuit model has an buffer * 1. buffer_existence_: specify if this circuit model has an buffer
* 2. buffer_circuit_model_name_: specify the name of circuit model for the buffer * 2. buffer_model_name_: specify the name of circuit model for the buffer
* 3. buffer_circuit_model_id_: specify the id of circuit model for the buffer * 3. buffer_model_id_: specify the id of circuit model for the buffer
* *
* ------ Pass-gate-related parameters ------ * ------ Pass-gate-related parameters ------
* 1. pass_gate_logic_circuit_model_name_: specify the name of circuit model for the pass gate logic * 1. pass_gate_logic_model_name_: specify the name of circuit model for the pass gate logic
* 2. pass_gate_logic_circuit_model_id_: specify the id of circuit model for the pass gate logic * 2. pass_gate_logic_model_id_: specify the id of circuit model for the pass gate logic
* *
* ------ Port information ------ * ------ Port information ------
* 1. port_ids_: unique id of ports belonging to a circuit model * 1. port_ids_: unique id of ports belonging to a circuit model
@ -129,10 +113,10 @@ typedef vtr::StrongId<circuit_edge_id_tag> CircuitEdgeId;
* 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches
* 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches
* 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches
* 13. port_circuit_model_name: the name of circuit model linked to the port * 13. port_model_name: the name of circuit model linked to the port
* 14. port_circuit_model_ids_: the Id of circuit model linked to the port * 14. port_model_ids_: the Id of circuit model linked to the port
* 15. port_inv_circuit_model_names_: the name of inverter circuit model linked to the port * 15. port_inv_model_names_: the name of inverter circuit model linked to the port
* 16. port_inv_circuit_model_ids_: the Id of inverter circuit model linked to the port * 16. port_inv_model_ids_: the Id of inverter circuit model linked to the port
* 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port
* 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used * 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used
* 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used * 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used
@ -196,19 +180,19 @@ typedef vtr::StrongId<circuit_edge_id_tag> CircuitEdgeId;
* *
* ------ Metal wire-related parameters ------ * ------ Metal wire-related parameters ------
* Note: only applicable to circuit models whose type is wires or channel wires * Note: only applicable to circuit models whose type is wires or channel wires
* 1. wire_types_: types of the metal wire for the circuit_model * 1. wire_types_: types of the metal wire for the model
* 2. wire_res_val_: resistance value of the metal wire for the circuit model * 2. wire_res_val_: resistance value of the metal wire for the circuit model
* 3. wire_cap_val_: capacitance value of the metal wire for the circuit model * 3. wire_cap_val_: capacitance value of the metal wire for the circuit model
* 4. wire_num_levels_: number of levels of the metal wire model for the circuit model * 4. wire_num_levels_: number of levels of the metal wire model for the circuit model
***********************************************************************/ ***********************************************************************/
class CircuitLibrary { class CircuitLibrary {
public: /* Types */ public: /* Types */
typedef vtr::vector<CircuitModelId, CircuitModelId>::const_iterator circuit_model_iterator; typedef vtr::vector<CircuitModelId, CircuitModelId>::const_iterator model_iterator;
typedef vtr::vector<CircuitModelId, std::string>::const_iterator circuit_model_string_iterator; typedef vtr::vector<CircuitModelId, std::string>::const_iterator model_string_iterator;
typedef vtr::vector<CircuitPortId, CircuitPortId>::const_iterator circuit_port_iterator; typedef vtr::vector<CircuitPortId, CircuitPortId>::const_iterator circuit_port_iterator;
typedef vtr::vector<CircuitEdgeId, CircuitEdgeId>::const_iterator circuit_edge_iterator; typedef vtr::vector<CircuitEdgeId, CircuitEdgeId>::const_iterator circuit_edge_iterator;
/* Create range */ /* Create range */
typedef vtr::Range<circuit_model_iterator> circuit_model_range; typedef vtr::Range<model_iterator> model_range;
typedef vtr::Range<circuit_port_iterator> circuit_port_range; typedef vtr::Range<circuit_port_iterator> circuit_port_range;
typedef vtr::Range<circuit_edge_iterator> circuit_edge_range; typedef vtr::Range<circuit_edge_iterator> circuit_edge_range;
/* local enumeration for buffer existence */ /* local enumeration for buffer existence */
@ -218,272 +202,272 @@ class CircuitLibrary {
public: /* Constructors */ public: /* Constructors */
CircuitLibrary(); CircuitLibrary();
public: /* Accessors: aggregates */ public: /* Accessors: aggregates */
circuit_model_range circuit_models() const; model_range models() const;
circuit_port_range ports(const CircuitModelId& circuit_model_id) const; circuit_port_range ports(const CircuitModelId& model_id) const;
std::vector<CircuitModelId> circuit_models_by_type(const enum e_spice_model_type& type) const; std::vector<CircuitModelId> models_by_type(const enum e_spice_model_type& type) const;
std::vector<CircuitPortId> ports_by_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_port_type& port_type) const; std::vector<CircuitPortId> ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type) const;
std::vector<CircuitPortId> ports_by_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; std::vector<CircuitPortId> ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const;
std::vector<CircuitPortId> input_ports(const CircuitModelId& circuit_model_id) const; std::vector<CircuitPortId> input_ports(const CircuitModelId& model_id) const;
std::vector<CircuitPortId> output_ports(const CircuitModelId& circuit_model_id) const; std::vector<CircuitPortId> output_ports(const CircuitModelId& model_id) const;
std::vector<size_t> pins(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; std::vector<size_t> pins(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
public: /* Public Accessors: Basic data query on Circuit Models*/ public: /* Public Accessors: Basic data query on Circuit Models*/
size_t num_circuit_models() const; size_t num_models() const;
enum e_spice_model_type circuit_model_type(const CircuitModelId& circuit_model_id) const; enum e_spice_model_type model_type(const CircuitModelId& model_id) const;
std::string circuit_model_name(const CircuitModelId& circuit_model_id) const; std::string model_name(const CircuitModelId& model_id) const;
std::string circuit_model_prefix(const CircuitModelId& circuit_model_id) const; std::string model_prefix(const CircuitModelId& model_id) const;
std::string circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id) const; std::string model_verilog_netlist(const CircuitModelId& model_id) const;
std::string circuit_model_spice_netlist(const CircuitModelId& circuit_model_id) const; std::string model_spice_netlist(const CircuitModelId& model_id) const;
bool circuit_model_is_default(const CircuitModelId& circuit_model_id) const; bool model_is_default(const CircuitModelId& model_id) const;
bool dump_structural_verilog(const CircuitModelId& circuit_model_id) const; bool dump_structural_verilog(const CircuitModelId& model_id) const;
bool dump_explicit_port_map(const CircuitModelId& circuit_model_id) const; bool dump_explicit_port_map(const CircuitModelId& model_id) const;
enum e_spice_model_design_tech design_tech_type(const CircuitModelId& circuit_model_id) const; enum e_spice_model_design_tech design_tech_type(const CircuitModelId& model_id) const;
bool is_power_gated(const CircuitModelId& circuit_model_id) const; bool is_power_gated(const CircuitModelId& model_id) const;
bool is_input_buffered(const CircuitModelId& circuit_model_id) const; bool is_input_buffered(const CircuitModelId& model_id) const;
bool is_output_buffered(const CircuitModelId& circuit_model_id) const; bool is_output_buffered(const CircuitModelId& model_id) const;
bool is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const; bool is_lut_intermediate_buffered(const CircuitModelId& model_id) const;
enum e_spice_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& circuit_model_id) const; enum e_spice_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& model_id) const;
enum e_spice_model_structure mux_structure(const CircuitModelId& circuit_model_id) const; enum e_spice_model_structure mux_structure(const CircuitModelId& model_id) const;
size_t mux_num_levels(const CircuitModelId& circuit_model_id) const; size_t mux_num_levels(const CircuitModelId& model_id) const;
bool mux_add_const_input(const CircuitModelId& circuit_model_id) const; bool mux_add_const_input(const CircuitModelId& model_id) const;
size_t mux_const_input_value(const CircuitModelId& circuit_model_id) const; size_t mux_const_input_value(const CircuitModelId& model_id) const;
public: /* Public Accessors: Basic data query on Circuit Ports*/ public: /* Public Accessors: Basic data query on Circuit Ports*/
bool is_input_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool is_input_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
bool is_output_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool is_output_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
CircuitPortId port(const CircuitModelId& circuit_model_id, const std::string& name) const; CircuitPortId port(const CircuitModelId& model_id, const std::string& name) const;
size_t num_ports(const CircuitModelId& circuit_model_id) const; size_t num_ports(const CircuitModelId& model_id) const;
size_t num_ports_by_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; size_t num_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const;
enum e_spice_model_port_type port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; enum e_spice_model_port_type port_type(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
size_t port_size(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; size_t port_size(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
std::string port_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; std::string port_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
std::string port_lib_name(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; std::string port_lib_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
std::string port_inv_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; std::string port_inv_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
size_t port_default_value(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; size_t port_default_value(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
bool port_is_mode_select(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool port_is_mode_select(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
bool port_is_global(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool port_is_global(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
bool port_is_reset(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool port_is_reset(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
bool port_is_set(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool port_is_set(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
bool port_is_config_enable(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool port_is_config_enable(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
bool port_is_prog(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool port_is_prog(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
public: /* Public Accessors: Methods to find circuit model */ public: /* Public Accessors: Methods to find circuit model */
CircuitModelId circuit_model(const char* name) const; CircuitModelId model(const char* name) const;
CircuitModelId circuit_model(const std::string& name) const; CircuitModelId model(const std::string& name) const;
CircuitModelId default_circuit_model(const enum e_spice_model_type& type) const; CircuitModelId default_model(const enum e_spice_model_type& type) const;
public: /* Public Accessors: Timing graph */ public: /* Public Accessors: Timing graph */
CircuitEdgeId edge(const CircuitModelId& circuit_model_id, CircuitEdgeId edge(const CircuitModelId& model_id,
const CircuitPortId& from_port, const size_t from_pin, const CircuitPortId& from_port, const size_t from_pin,
const CircuitPortId& to_port, const size_t to_pin); const CircuitPortId& to_port, const size_t to_pin);
public: /* Public Mutators */ public: /* Public Mutators */
CircuitModelId add_circuit_model(); CircuitModelId add_model();
/* Fundamental information */ /* Fundamental information */
void set_circuit_model_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_type& type); void set_model_type(const CircuitModelId& model_id, const enum e_spice_model_type& type);
void set_circuit_model_name(const CircuitModelId& circuit_model_id, const std::string& name); void set_model_name(const CircuitModelId& model_id, const std::string& name);
void set_circuit_model_prefix(const CircuitModelId& circuit_model_id, const std::string& prefix); void set_model_prefix(const CircuitModelId& model_id, const std::string& prefix);
void set_circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id, const std::string& verilog_netlist); void set_model_verilog_netlist(const CircuitModelId& model_id, const std::string& verilog_netlist);
void set_circuit_model_spice_netlist(const CircuitModelId& circuit_model_id, const std::string& spice_netlist); void set_model_spice_netlist(const CircuitModelId& model_id, const std::string& spice_netlist);
void set_circuit_model_is_default(const CircuitModelId& circuit_model_id, const bool& is_default); void set_model_is_default(const CircuitModelId& model_id, const bool& is_default);
/* Verilog generator options */ /* Verilog generator options */
void set_circuit_model_dump_structural_verilog(const CircuitModelId& circuit_model_id, const bool& dump_structural_verilog); void set_model_dump_structural_verilog(const CircuitModelId& model_id, const bool& dump_structural_verilog);
void set_circuit_model_dump_explicit_port_map(const CircuitModelId& circuit_model_id, const bool& dump_explicit_port_map); void set_model_dump_explicit_port_map(const CircuitModelId& model_id, const bool& dump_explicit_port_map);
/* Design technology information */ /* Design technology information */
void set_circuit_model_design_tech_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_design_tech& design_tech_type); void set_model_design_tech_type(const CircuitModelId& model_id, const enum e_spice_model_design_tech& design_tech_type);
void set_circuit_model_is_power_gated(const CircuitModelId& circuit_model_id, const bool& is_power_gated); void set_model_is_power_gated(const CircuitModelId& model_id, const bool& is_power_gated);
/* Buffer existence */ /* Buffer existence */
void set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id, void set_model_input_buffer(const CircuitModelId& model_id,
const bool& existence, const std::string& circuit_model_name); const bool& existence, const std::string& model_name);
void set_circuit_model_output_buffer(const CircuitModelId& circuit_model_id, void set_model_output_buffer(const CircuitModelId& model_id,
const bool& existence, const std::string& circuit_model_name); const bool& existence, const std::string& model_name);
void set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id, void set_model_lut_input_buffer(const CircuitModelId& model_id,
const bool& existence, const std::string& circuit_model_name); const bool& existence, const std::string& model_name);
void set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id, void set_model_lut_input_inverter(const CircuitModelId& model_id,
const bool& existence, const std::string& circuit_model_name); const bool& existence, const std::string& model_name);
void set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, void set_model_lut_intermediate_buffer(const CircuitModelId& model_id,
const bool& existence, const std::string& circuit_model_name); const bool& existence, const std::string& model_name);
void set_circuit_model_lut_intermediate_buffer_location_map(const CircuitModelId& circuit_model_id, void set_model_lut_intermediate_buffer_location_map(const CircuitModelId& model_id,
const std::string& location_map); const std::string& location_map);
/* Pass-gate-related parameters */ /* Pass-gate-related parameters */
void set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name); void set_model_pass_gate_logic(const CircuitModelId& model_id, const std::string& model_name);
/* Port information */ /* Port information */
CircuitPortId add_circuit_model_port(const CircuitModelId& circuit_model_id); CircuitPortId add_model_port(const CircuitModelId& model_id);
void set_port_type(const CircuitModelId& circuit_model_id, void set_port_type(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const enum e_spice_model_port_type& port_type); const enum e_spice_model_port_type& port_type);
void set_port_size(const CircuitModelId& circuit_model_id, void set_port_size(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const size_t& port_size); const size_t& port_size);
void set_port_prefix(const CircuitModelId& circuit_model_id, void set_port_prefix(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const std::string& port_prefix); const std::string& port_prefix);
void set_port_lib_name(const CircuitModelId& circuit_model_id, void set_port_lib_name(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const std::string& lib_name); const std::string& lib_name);
void set_port_inv_prefix(const CircuitModelId& circuit_model_id, void set_port_inv_prefix(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const std::string& inv_prefix); const std::string& inv_prefix);
void set_port_default_value(const CircuitModelId& circuit_model_id, void set_port_default_value(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const size_t& default_val); const size_t& default_val);
void set_port_is_mode_select(const CircuitModelId& circuit_model_id, void set_port_is_mode_select(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const bool& is_mode_select); const bool& is_mode_select);
void set_port_is_global(const CircuitModelId& circuit_model_id, void set_port_is_global(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const bool& is_global); const bool& is_global);
void set_port_is_reset(const CircuitModelId& circuit_model_id, void set_port_is_reset(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const bool& is_reset); const bool& is_reset);
void set_port_is_set(const CircuitModelId& circuit_model_id, void set_port_is_set(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const bool& is_set); const bool& is_set);
void set_port_is_config_enable(const CircuitModelId& circuit_model_id, void set_port_is_config_enable(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const bool& is_config_enable); const bool& is_config_enable);
void set_port_is_prog(const CircuitModelId& circuit_model_id, void set_port_is_prog(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const bool& is_prog); const bool& is_prog);
void set_port_circuit_model_name(const CircuitModelId& circuit_model_id, void set_port_model_name(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const std::string& circuit_model_name); const std::string& model_name);
void set_port_circuit_model_id(const CircuitModelId& circuit_model_id, void set_port_model_id(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const CircuitModelId& port_circuit_model_id); const CircuitModelId& port_model_id);
void set_port_inv_circuit_model_name(const CircuitModelId& circuit_model_id, void set_port_inv_model_name(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const std::string& inv_circuit_model_name); const std::string& inv_model_name);
void set_port_inv_circuit_model_id(const CircuitModelId& circuit_model_id, void set_port_inv_model_id(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const CircuitModelId& inv_circuit_model_id); const CircuitModelId& inv_model_id);
void set_port_tri_state_map(const CircuitModelId& circuit_model_id, void set_port_tri_state_map(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const std::string& tri_state_map); const std::string& tri_state_map);
void set_port_lut_frac_level(const CircuitModelId& circuit_model_id, void set_port_lut_frac_level(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const size_t& lut_frac_level); const size_t& lut_frac_level);
void set_port_lut_output_mask(const CircuitModelId& circuit_model_id, void set_port_lut_output_mask(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const std::vector<size_t>& lut_output_masks); const std::vector<size_t>& lut_output_masks);
void set_port_sram_orgz(const CircuitModelId& circuit_model_id, void set_port_sram_orgz(const CircuitModelId& model_id,
const CircuitPortId& circuit_port_id, const CircuitPortId& circuit_port_id,
const enum e_sram_orgz& sram_orgz); const enum e_sram_orgz& sram_orgz);
/* Delay information */ /* Delay information */
void add_delay_info(const CircuitModelId& circuit_model_id, void add_delay_info(const CircuitModelId& model_id,
const enum spice_model_delay_type& delay_type); const enum spice_model_delay_type& delay_type);
void set_delay_in_port_names(const CircuitModelId& circuit_model_id, void set_delay_in_port_names(const CircuitModelId& model_id,
const enum spice_model_delay_type& delay_type, const enum spice_model_delay_type& delay_type,
const std::string& in_port_names); const std::string& in_port_names);
void set_delay_out_port_names(const CircuitModelId& circuit_model_id, void set_delay_out_port_names(const CircuitModelId& model_id,
const enum spice_model_delay_type& delay_type, const enum spice_model_delay_type& delay_type,
const std::string& out_port_names); const std::string& out_port_names);
void set_delay_values(const CircuitModelId& circuit_model_id, void set_delay_values(const CircuitModelId& model_id,
const enum spice_model_delay_type& delay_type, const enum spice_model_delay_type& delay_type,
const std::string& delay_values); const std::string& delay_values);
/* Buffer/Inverter-related parameters */ /* Buffer/Inverter-related parameters */
void set_buffer_type(const CircuitModelId& circuit_model_id, void set_buffer_type(const CircuitModelId& model_id,
const enum e_spice_model_buffer_type& buffer_type); const enum e_spice_model_buffer_type& buffer_type);
void set_buffer_size(const CircuitModelId& circuit_model_id, void set_buffer_size(const CircuitModelId& model_id,
const float& buffer_size); const float& buffer_size);
void set_buffer_num_levels(const CircuitModelId& circuit_model_id, void set_buffer_num_levels(const CircuitModelId& model_id,
const size_t& num_levels); const size_t& num_levels);
void set_buffer_f_per_stage(const CircuitModelId& circuit_model_id, void set_buffer_f_per_stage(const CircuitModelId& model_id,
const size_t& f_per_stage); const size_t& f_per_stage);
/* Pass-gate-related parameters */ /* Pass-gate-related parameters */
void set_pass_gate_logic_type(const CircuitModelId& circuit_model_id, void set_pass_gate_logic_type(const CircuitModelId& model_id,
const enum e_spice_model_pass_gate_logic_type& pass_gate_logic_type); const enum e_spice_model_pass_gate_logic_type& pass_gate_logic_type);
void set_pass_gate_logic_nmos_size(const CircuitModelId& circuit_model_id, void set_pass_gate_logic_nmos_size(const CircuitModelId& model_id,
const float& nmos_size); const float& nmos_size);
void set_pass_gate_logic_pmos_size(const CircuitModelId& circuit_model_id, void set_pass_gate_logic_pmos_size(const CircuitModelId& model_id,
const float& pmos_size); const float& pmos_size);
/* Multiplexer-related parameters */ /* Multiplexer-related parameters */
void set_mux_structure(const CircuitModelId& circuit_model_id, void set_mux_structure(const CircuitModelId& model_id,
const enum e_spice_model_structure& mux_structure); const enum e_spice_model_structure& mux_structure);
void set_mux_num_levels(const CircuitModelId& circuit_model_id, void set_mux_num_levels(const CircuitModelId& model_id,
const size_t& num_levels); const size_t& num_levels);
void set_mux_const_input_value(const CircuitModelId& circuit_model_id, void set_mux_const_input_value(const CircuitModelId& model_id,
const size_t& const_input_value); const size_t& const_input_value);
void set_mux_use_local_encoder(const CircuitModelId& circuit_model_id, void set_mux_use_local_encoder(const CircuitModelId& model_id,
const bool& use_local_encoder); const bool& use_local_encoder);
void set_mux_use_advanced_rram_design(const CircuitModelId& circuit_model_id, void set_mux_use_advanced_rram_design(const CircuitModelId& model_id,
const bool& use_advanced_rram_design); const bool& use_advanced_rram_design);
/* LUT-related parameters */ /* LUT-related parameters */
void set_lut_is_fracturable(const CircuitModelId& circuit_model_id, void set_lut_is_fracturable(const CircuitModelId& model_id,
const bool& is_fracturable); const bool& is_fracturable);
/* Gate-related parameters */ /* Gate-related parameters */
void set_gate_type(const CircuitModelId& circuit_model_id, void set_gate_type(const CircuitModelId& model_id,
const enum e_spice_model_gate_type& gate_type); const enum e_spice_model_gate_type& gate_type);
/* RRAM-related design technology information */ /* RRAM-related design technology information */
void set_rram_rlrs(const CircuitModelId& circuit_model_id, void set_rram_rlrs(const CircuitModelId& model_id,
const float& rlrs); const float& rlrs);
void set_rram_rhrs(const CircuitModelId& circuit_model_id, void set_rram_rhrs(const CircuitModelId& model_id,
const float& rhrs); const float& rhrs);
void set_rram_wprog_set_nmos(const CircuitModelId& circuit_model_id, void set_rram_wprog_set_nmos(const CircuitModelId& model_id,
const float& wprog_set_nmos); const float& wprog_set_nmos);
void set_rram_wprog_set_pmos(const CircuitModelId& circuit_model_id, void set_rram_wprog_set_pmos(const CircuitModelId& model_id,
const float& wprog_set_pmos); const float& wprog_set_pmos);
void set_rram_wprog_reset_nmos(const CircuitModelId& circuit_model_id, void set_rram_wprog_reset_nmos(const CircuitModelId& model_id,
const float& wprog_reset_nmos); const float& wprog_reset_nmos);
void set_rram_wprog_reset_pmos(const CircuitModelId& circuit_model_id, void set_rram_wprog_reset_pmos(const CircuitModelId& model_id,
const float& wprog_reset_pmos); const float& wprog_reset_pmos);
/* Wire parameters */ /* Wire parameters */
void set_wire_type(const CircuitModelId& circuit_model_id, void set_wire_type(const CircuitModelId& model_id,
const enum e_wire_model_type& wire_type); const enum e_wire_model_type& wire_type);
void set_wire_r(const CircuitModelId& circuit_model_id, void set_wire_r(const CircuitModelId& model_id,
const float& r_val); const float& r_val);
void set_wire_c(const CircuitModelId& circuit_model_id, void set_wire_c(const CircuitModelId& model_id,
const float& c_val); const float& c_val);
void set_wire_num_levels(const CircuitModelId& circuit_model_id, void set_wire_num_levels(const CircuitModelId& model_id,
const size_t& num_level); const size_t& num_level);
public: /* Public Mutators: builders */ public: /* Public Mutators: builders */
void set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& circuit_model_name); void set_model_buffer(const CircuitModelId& model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& model_name);
void link_port_circuit_model(const CircuitModelId& circuit_model_id); void link_port_model(const CircuitModelId& model_id);
void link_port_inv_circuit_model(const CircuitModelId& circuit_model_id); void link_port_inv_model(const CircuitModelId& model_id);
void link_port_circuit_models(const CircuitModelId& circuit_model_id); void link_port_models(const CircuitModelId& model_id);
void link_buffer_circuit_model(const CircuitModelId& circuit_model_id); void link_buffer_model(const CircuitModelId& model_id);
void link_pass_gate_logic_circuit_model(const CircuitModelId& circuit_model_id); void link_pass_gate_logic_model(const CircuitModelId& model_id);
void build_circuit_model_links(); void build_model_links();
void build_circuit_model_timing_graph(const CircuitModelId& circuit_model_id); void build_model_timing_graph(const CircuitModelId& model_id);
void build_timing_graphs(); void build_timing_graphs();
public: /* Internal mutators: build timing graphs */ public: /* Internal mutators: build timing graphs */
void add_edge(const CircuitModelId& circuit_model_id, void add_edge(const CircuitModelId& model_id,
const CircuitPortId& from_port, const size_t& from_pin, const CircuitPortId& from_port, const size_t& from_pin,
const CircuitPortId& to_port, const size_t& to_pin); const CircuitPortId& to_port, const size_t& to_pin);
void set_edge_delay(const CircuitModelId& circuit_model_id, void set_edge_delay(const CircuitModelId& model_id,
const CircuitEdgeId& circuit_edge_id, const CircuitEdgeId& circuit_edge_id,
const enum spice_model_delay_type& delay_type, const enum spice_model_delay_type& delay_type,
const float& delay_value); const float& delay_value);
/* validate the circuit_edge_id */ /* validate the circuit_edge_id */
void set_timing_graph_delays(const CircuitModelId& circuit_model_id); void set_timing_graph_delays(const CircuitModelId& model_id);
public: /* Internal mutators: build fast look-ups */ public: /* Internal mutators: build fast look-ups */
void build_circuit_model_lookup(); void build_model_lookup();
void build_circuit_model_port_lookup(const CircuitModelId& circuit_model_id); void build_model_port_lookup(const CircuitModelId& model_id);
private: /* Internal invalidators/validators */ private: /* Internal invalidators/validators */
/* Validators */ /* Validators */
bool valid_circuit_model_id(const CircuitModelId& circuit_model_id) const; bool valid_model_id(const CircuitModelId& model_id) const;
bool valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; bool valid_circuit_port_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const;
bool valid_circuit_pin_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const; bool valid_circuit_pin_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const;
bool valid_delay_type(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type) const; bool valid_delay_type(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) const;
bool valid_circuit_edge_id(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id) const; bool valid_circuit_edge_id(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id) const;
bool valid_mux_const_input_value(const size_t& const_input_value) const; bool valid_mux_const_input_value(const size_t& const_input_value) const;
/* Invalidators */ /* Invalidators */
void invalidate_circuit_model_lookup() const; void invalidate_model_lookup() const;
void invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const; void invalidate_model_port_lookup(const CircuitModelId& model_id) const;
void invalidate_circuit_model_timing_graph(const CircuitModelId& circuit_model_id); void invalidate_model_timing_graph(const CircuitModelId& model_id);
private: /* Internal data */ private: /* Internal data */
/* Fundamental information */ /* Fundamental information */
vtr::vector<CircuitModelId, CircuitModelId> circuit_model_ids_; vtr::vector<CircuitModelId, CircuitModelId> model_ids_;
vtr::vector<CircuitModelId, enum e_spice_model_type> circuit_model_types_; vtr::vector<CircuitModelId, enum e_spice_model_type> model_types_;
vtr::vector<CircuitModelId, std::string> circuit_model_names_; vtr::vector<CircuitModelId, std::string> model_names_;
vtr::vector<CircuitModelId, std::string> circuit_model_prefix_; vtr::vector<CircuitModelId, std::string> model_prefix_;
vtr::vector<CircuitModelId, std::string> circuit_model_verilog_netlists_; vtr::vector<CircuitModelId, std::string> model_verilog_netlists_;
vtr::vector<CircuitModelId, std::string> circuit_model_spice_netlists_; vtr::vector<CircuitModelId, std::string> model_spice_netlists_;
vtr::vector<CircuitModelId, bool> circuit_model_is_default_; vtr::vector<CircuitModelId, bool> model_is_default_;
/* fast look-up for circuit models to categorize by types /* fast look-up for circuit models to categorize by types
* [type][num_ids] * [type][num_ids]
* Important: we force the default circuit model in the first element for each type * Important: we force the default circuit model in the first element for each type
*/ */
typedef std::vector<std::vector<CircuitModelId>> CircuitModelLookup; typedef std::vector<std::vector<CircuitModelId>> CircuitModelLookup;
mutable CircuitModelLookup circuit_model_lookup_; /* [circuit_model_type][circuit_model_ids] */ mutable CircuitModelLookup model_lookup_; /* [model_type][model_ids] */
typedef std::vector<std::vector<std::vector<CircuitPortId>>> CircuitModelPortLookup; typedef std::vector<std::vector<std::vector<CircuitPortId>>> CircuitModelPortLookup;
mutable CircuitModelPortLookup circuit_model_port_lookup_; /* [circuit_model_id][port_type][port_ids] */ mutable CircuitModelPortLookup model_port_lookup_; /* [model_id][port_type][port_ids] */
/* Verilog generator options */ /* Verilog generator options */
vtr::vector<CircuitModelId, bool> dump_structural_verilog_; vtr::vector<CircuitModelId, bool> dump_structural_verilog_;
@ -495,13 +479,13 @@ class CircuitLibrary {
/* Buffer existence */ /* Buffer existence */
vtr::vector<CircuitModelId, std::vector<bool>> buffer_existence_; vtr::vector<CircuitModelId, std::vector<bool>> buffer_existence_;
vtr::vector<CircuitModelId, std::vector<std::string>> buffer_circuit_model_names_; vtr::vector<CircuitModelId, std::vector<std::string>> buffer_model_names_;
vtr::vector<CircuitModelId, std::vector<CircuitModelId>> buffer_circuit_model_ids_; vtr::vector<CircuitModelId, std::vector<CircuitModelId>> buffer_model_ids_;
vtr::vector<CircuitModelId, std::vector<std::string>> buffer_location_maps_; vtr::vector<CircuitModelId, std::vector<std::string>> buffer_location_maps_;
/* Pass-gate-related parameters */ /* Pass-gate-related parameters */
vtr::vector<CircuitModelId, std::string> pass_gate_logic_circuit_model_names_; vtr::vector<CircuitModelId, std::string> pass_gate_logic_model_names_;
vtr::vector<CircuitModelId, CircuitModelId> pass_gate_logic_circuit_model_ids_; vtr::vector<CircuitModelId, CircuitModelId> pass_gate_logic_model_ids_;
/* Port information */ /* Port information */
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, CircuitPortId>> port_ids_; vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, CircuitPortId>> port_ids_;
@ -517,10 +501,10 @@ class CircuitLibrary {
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_set_; vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_set_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_config_enable_; vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_config_enable_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_prog_; vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, bool>> port_is_prog_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_circuit_model_names_; vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_model_names_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, CircuitModelId>> port_circuit_model_ids_; vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, CircuitModelId>> port_model_ids_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_inv_circuit_model_names_; vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_inv_model_names_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, CircuitModelId>> port_inv_circuit_model_ids_; vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, CircuitModelId>> port_inv_model_ids_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_tri_state_maps_; vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::string>> port_tri_state_maps_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, size_t>> port_lut_frac_level_; vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, size_t>> port_lut_frac_level_;
vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::vector<size_t>>> port_lut_output_masks_; vtr::vector<CircuitModelId, vtr::vector<CircuitPortId, std::vector<size_t>>> port_lut_output_masks_;

21
vpr7_x2p/libarchfpga/SRC/circuit_library_fwd.h Normal file
View File

@ -0,0 +1,21 @@
/************************************************************************
* A header file for CircuitLibrary class, including critical data declaration
* Please include this file only for using any CircuitLibrary data structure
* Refer to circuit_library.h for more details
***********************************************************************/
/************************************************************************
* Create strong id for Circuit Models/Ports to avoid illegal type casting
***********************************************************************/
#include "vtr_strong_id.h"
struct circuit_model_id_tag;
struct circuit_port_id_tag;
struct circuit_edge_id_tag;
typedef vtr::StrongId<circuit_model_id_tag> CircuitModelId;
typedef vtr::StrongId<circuit_port_id_tag> CircuitPortId;
typedef vtr::StrongId<circuit_edge_id_tag> CircuitEdgeId;
/* Short declaration of class */
class CircuitLibrary;

44
vpr7_x2p/libarchfpga/SRC/read_xml_spice.c
View File

@ -1573,38 +1573,38 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m
/* Go spice_model by spice_model */ /* Go spice_model by spice_model */
for (int imodel = 0; imodel < num_spice_model; ++imodel) { for (int imodel = 0; imodel < num_spice_model; ++imodel) {
/* Add a spice model to the circuit_lib */ /* Add a spice model to the circuit_lib */
CircuitModelId model_id = circuit_lib.add_circuit_model(); CircuitModelId model_id = circuit_lib.add_model();
/* Fill fundamental attributes */ /* Fill fundamental attributes */
/* Basic information*/ /* Basic information*/
circuit_lib.set_circuit_model_type(model_id, spice_models[imodel].type); circuit_lib.set_model_type(model_id, spice_models[imodel].type);
std::string name(spice_models[imodel].name); std::string name(spice_models[imodel].name);
circuit_lib.set_circuit_model_name(model_id, name); circuit_lib.set_model_name(model_id, name);
std::string prefix(spice_models[imodel].prefix); std::string prefix(spice_models[imodel].prefix);
circuit_lib.set_circuit_model_prefix(model_id, prefix); circuit_lib.set_model_prefix(model_id, prefix);
if (NULL != spice_models[imodel].verilog_netlist) { if (NULL != spice_models[imodel].verilog_netlist) {
std::string verilog_netlist(spice_models[imodel].verilog_netlist); std::string verilog_netlist(spice_models[imodel].verilog_netlist);
circuit_lib.set_circuit_model_verilog_netlist(model_id, verilog_netlist); circuit_lib.set_model_verilog_netlist(model_id, verilog_netlist);
} }
if (NULL != spice_models[imodel].model_netlist) { if (NULL != spice_models[imodel].model_netlist) {
std::string spice_netlist(spice_models[imodel].model_netlist); std::string spice_netlist(spice_models[imodel].model_netlist);
circuit_lib.set_circuit_model_spice_netlist(model_id, spice_netlist); circuit_lib.set_model_spice_netlist(model_id, spice_netlist);
} }
circuit_lib.set_circuit_model_is_default(model_id, 0 != spice_models[imodel].is_default); circuit_lib.set_model_is_default(model_id, 0 != spice_models[imodel].is_default);
/* Verilog generatioin options */ /* Verilog generatioin options */
circuit_lib.set_circuit_model_dump_structural_verilog(model_id, TRUE == spice_models[imodel].dump_structural_verilog); circuit_lib.set_model_dump_structural_verilog(model_id, TRUE == spice_models[imodel].dump_structural_verilog);
circuit_lib.set_circuit_model_dump_explicit_port_map(model_id, TRUE == spice_models[imodel].dump_explicit_port_map); circuit_lib.set_model_dump_explicit_port_map(model_id, TRUE == spice_models[imodel].dump_explicit_port_map);
/* Design technology information */ /* Design technology information */
circuit_lib.set_circuit_model_design_tech_type(model_id, spice_models[imodel].design_tech); circuit_lib.set_model_design_tech_type(model_id, spice_models[imodel].design_tech);
circuit_lib.set_circuit_model_is_power_gated(model_id, TRUE == spice_models[imodel].design_tech_info.power_gated); circuit_lib.set_model_is_power_gated(model_id, TRUE == spice_models[imodel].design_tech_info.power_gated);
/* Buffer linking information */ /* Buffer linking information */
if (NULL != spice_models[imodel].input_buffer) { if (NULL != spice_models[imodel].input_buffer) {
@ -1612,28 +1612,28 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m
if (NULL != spice_models[imodel].input_buffer->spice_model_name) { if (NULL != spice_models[imodel].input_buffer->spice_model_name) {
model_name = spice_models[imodel].input_buffer->spice_model_name; model_name = spice_models[imodel].input_buffer->spice_model_name;
} }
circuit_lib.set_circuit_model_input_buffer(model_id, 0 != spice_models[imodel].input_buffer->exist, model_name); circuit_lib.set_model_input_buffer(model_id, 0 != spice_models[imodel].input_buffer->exist, model_name);
} }
if (NULL != spice_models[imodel].output_buffer) { if (NULL != spice_models[imodel].output_buffer) {
std::string model_name; std::string model_name;
if (NULL != spice_models[imodel].output_buffer->spice_model_name) { if (NULL != spice_models[imodel].output_buffer->spice_model_name) {
model_name = spice_models[imodel].output_buffer->spice_model_name; model_name = spice_models[imodel].output_buffer->spice_model_name;
} }
circuit_lib.set_circuit_model_output_buffer(model_id, 0 != spice_models[imodel].output_buffer->exist, model_name); circuit_lib.set_model_output_buffer(model_id, 0 != spice_models[imodel].output_buffer->exist, model_name);
} }
if (NULL != spice_models[imodel].lut_input_buffer) { if (NULL != spice_models[imodel].lut_input_buffer) {
std::string model_name; std::string model_name;
if (NULL != spice_models[imodel].lut_input_buffer->spice_model_name) { if (NULL != spice_models[imodel].lut_input_buffer->spice_model_name) {
model_name = spice_models[imodel].lut_input_buffer->spice_model_name; model_name = spice_models[imodel].lut_input_buffer->spice_model_name;
} }
circuit_lib.set_circuit_model_lut_input_buffer(model_id, 0 != spice_models[imodel].lut_input_buffer->exist, model_name); circuit_lib.set_model_lut_input_buffer(model_id, 0 != spice_models[imodel].lut_input_buffer->exist, model_name);
} }
if (NULL != spice_models[imodel].lut_input_inverter) { if (NULL != spice_models[imodel].lut_input_inverter) {
std::string model_name; std::string model_name;
if (NULL != spice_models[imodel].lut_input_inverter->spice_model_name) { if (NULL != spice_models[imodel].lut_input_inverter->spice_model_name) {
model_name = spice_models[imodel].lut_input_inverter->spice_model_name; model_name = spice_models[imodel].lut_input_inverter->spice_model_name;
} }
circuit_lib.set_circuit_model_lut_input_inverter(model_id, 0 != spice_models[imodel].lut_input_inverter->exist, model_name); circuit_lib.set_model_lut_input_inverter(model_id, 0 != spice_models[imodel].lut_input_inverter->exist, model_name);
} }
if ( (NULL != spice_models[imodel].lut_intermediate_buffer) if ( (NULL != spice_models[imodel].lut_intermediate_buffer)
&& (1 == spice_models[imodel].lut_intermediate_buffer->exist) ) { && (1 == spice_models[imodel].lut_intermediate_buffer->exist) ) {
@ -1641,19 +1641,19 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m
if (NULL != spice_models[imodel].lut_intermediate_buffer->spice_model_name) { if (NULL != spice_models[imodel].lut_intermediate_buffer->spice_model_name) {
model_name = spice_models[imodel].lut_intermediate_buffer->spice_model_name; model_name = spice_models[imodel].lut_intermediate_buffer->spice_model_name;
} }
circuit_lib.set_circuit_model_lut_intermediate_buffer(model_id, 0 != spice_models[imodel].lut_intermediate_buffer->exist, model_name); circuit_lib.set_model_lut_intermediate_buffer(model_id, 0 != spice_models[imodel].lut_intermediate_buffer->exist, model_name);
std::string model_location_map; std::string model_location_map;
if (NULL != spice_models[imodel].lut_intermediate_buffer->location_map) { if (NULL != spice_models[imodel].lut_intermediate_buffer->location_map) {
model_location_map = spice_models[imodel].lut_intermediate_buffer->location_map; model_location_map = spice_models[imodel].lut_intermediate_buffer->location_map;
} }
circuit_lib.set_circuit_model_lut_intermediate_buffer_location_map(model_id, model_location_map); circuit_lib.set_model_lut_intermediate_buffer_location_map(model_id, model_location_map);
} }
/* Pass-gate-logic linking information */ /* Pass-gate-logic linking information */
if (NULL != spice_models[imodel].pass_gate_logic) { if (NULL != spice_models[imodel].pass_gate_logic) {
std::string model_name(spice_models[imodel].pass_gate_logic->spice_model_name); std::string model_name(spice_models[imodel].pass_gate_logic->spice_model_name);
circuit_lib.set_circuit_model_pass_gate_logic(model_id, model_name); circuit_lib.set_model_pass_gate_logic(model_id, model_name);
} }
/* Buffer information */ /* Buffer information */
@ -1728,7 +1728,7 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m
/* Ports */ /* Ports */
for (int iport = 0; iport < spice_models[imodel].num_port; ++iport) { for (int iport = 0; iport < spice_models[imodel].num_port; ++iport) {
CircuitPortId port_id = circuit_lib.add_circuit_model_port(model_id); CircuitPortId port_id = circuit_lib.add_model_port(model_id);
/* Fill fundamental attributes */ /* Fill fundamental attributes */
circuit_lib.set_port_type(model_id, port_id, spice_models[imodel].ports[iport].type); circuit_lib.set_port_type(model_id, port_id, spice_models[imodel].ports[iport].type);
@ -1756,12 +1756,12 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m
if (NULL != spice_models[imodel].ports[iport].spice_model_name) { if (NULL != spice_models[imodel].ports[iport].spice_model_name) {
std::string port_model_name(spice_models[imodel].ports[iport].spice_model_name); std::string port_model_name(spice_models[imodel].ports[iport].spice_model_name);
circuit_lib.set_port_circuit_model_name(model_id, port_id, port_model_name); circuit_lib.set_port_model_name(model_id, port_id, port_model_name);
} }
if (NULL != spice_models[imodel].ports[iport].inv_spice_model_name) { if (NULL != spice_models[imodel].ports[iport].inv_spice_model_name) {
std::string port_inv_model_name(spice_models[imodel].ports[iport].inv_spice_model_name); std::string port_inv_model_name(spice_models[imodel].ports[iport].inv_spice_model_name);
circuit_lib.set_port_inv_circuit_model_name(model_id, port_id, port_inv_model_name); circuit_lib.set_port_inv_model_name(model_id, port_id, port_inv_model_name);
} }
if (NULL != spice_models[imodel].ports[iport].tri_state_map) { if (NULL != spice_models[imodel].ports[iport].tri_state_map) {
@ -1786,7 +1786,7 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m
} }
/* Build circuit_model links */ /* Build circuit_model links */
circuit_lib.build_circuit_model_links(); circuit_lib.build_model_links();
/* Build timing graph */ /* Build timing graph */
circuit_lib.build_timing_graphs(); circuit_lib.build_timing_graphs();

6
vpr7_x2p/vpr/SRC/device/mux_graph.cpp
View File

@ -553,8 +553,8 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model, const CircuitModelId& circuit_model,
const size_t& mux_size) { const size_t& mux_size) {
/* Make sure this model is a MUX */ /* Make sure this model is a MUX */
VTR_ASSERT((SPICE_MODEL_MUX == circuit_lib.circuit_model_type(circuit_model)) VTR_ASSERT((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model))
|| (SPICE_MODEL_LUT == circuit_lib.circuit_model_type(circuit_model)) ); || (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) );
/* Make sure mux_size is valid */ /* Make sure mux_size is valid */
VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size));
@ -594,7 +594,7 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib,
default: default:
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d]) Invalid multiplexer structure for circuit model (name=%s)!\n", "(File:%s, [LINE%d]) Invalid multiplexer structure for circuit model (name=%s)!\n",
__FILE__, __LINE__, circuit_lib.circuit_model_name(circuit_model)); __FILE__, __LINE__, circuit_lib.model_name(circuit_model));
exit(1); exit(1);
} }

8
vpr7_x2p/vpr/SRC/device/mux_utils.cpp
View File

@ -28,10 +28,10 @@ size_t find_mux_implementation_num_inputs(const CircuitLibrary& circuit_lib,
/* Should be either MUX or LUT /* Should be either MUX or LUT
* LUTs do have an tree-like MUX, but there is no need for a constant input! * LUTs do have an tree-like MUX, but there is no need for a constant input!
*/ */
VTR_ASSERT ((SPICE_MODEL_MUX == circuit_lib.circuit_model_type(circuit_model)) VTR_ASSERT ((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model))
|| (SPICE_MODEL_LUT == circuit_lib.circuit_model_type(circuit_model)) ); || (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) );
if (SPICE_MODEL_LUT == circuit_lib.circuit_model_type(circuit_model)) { if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) {
return mux_size; return mux_size;
} }
@ -147,7 +147,7 @@ MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llis
/* Build a MUX graph for the model */ /* Build a MUX graph for the model */
/* Find the circuit model id by the name */ /* Find the circuit model id by the name */
CircuitModelId circuit_model = circuit_lib.circuit_model(cur_spice_mux_model->spice_model->name); CircuitModelId circuit_model = circuit_lib.model(cur_spice_mux_model->spice_model->name);
mux_lib.add_mux(circuit_lib, circuit_model, cur_spice_mux_model->size); mux_lib.add_mux(circuit_lib, circuit_model, cur_spice_mux_model->size);
/* Move on to the next*/ /* Move on to the next*/

46
vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp
View File

@ -81,31 +81,31 @@
CircuitModelId link_circuit_model_by_name_and_type(const char* circuit_model_name, CircuitModelId link_circuit_model_by_name_and_type(const char* circuit_model_name,
const CircuitLibrary& circuit_lib, const CircuitLibrary& circuit_lib,
const enum e_spice_model_type& model_type) { const enum e_spice_model_type& model_type) {
CircuitModelId circuit_model = CIRCUIT_MODEL_OPEN_ID; CircuitModelId circuit_model = CircuitModelId::INVALID();
/* If the circuit_model_name is not defined, we use the default*/ /* If the circuit_model_name is not defined, we use the default*/
if (NULL == circuit_model_name) { if (NULL == circuit_model_name) {
circuit_model = circuit_lib.default_circuit_model(model_type); circuit_model = circuit_lib.default_model(model_type);
} else { } else {
circuit_model = circuit_lib.circuit_model(circuit_model_name); circuit_model = circuit_lib.model(circuit_model_name);
} }
/* Check the circuit model, we should have one! */ /* Check the circuit model, we should have one! */
if (CIRCUIT_MODEL_OPEN_ID == circuit_model) { if (CircuitModelId::INVALID() == circuit_model) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s,LINE[%d]) Fail to find a defined circuit model called %s!\n", "(File:%s,LINE[%d]) Fail to find a defined circuit model called %s!\n",
__FILE__, __LINE__, __FILE__, __LINE__,
circuit_lib.circuit_model_name(circuit_model).c_str()); circuit_lib.model_name(circuit_model).c_str());
return circuit_model; /* Return here, no need to check the model_type */ return circuit_model; /* Return here, no need to check the model_type */
} }
/* Check the type of circuit model, make sure it is the one we want */ /* Check the type of circuit model, make sure it is the one we want */
if (model_type != circuit_lib.circuit_model_type(circuit_model)) { if (model_type != circuit_lib.model_type(circuit_model)) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s,LINE[%d]) Invalid type when trying to find circuit model called %s! Expect %s but found %s!\n", "(File:%s,LINE[%d]) Invalid type when trying to find circuit model called %s! Expect %s but found %s!\n",
__FILE__, __LINE__, __FILE__, __LINE__,
circuit_model_name, circuit_model_name,
CIRCUIT_MODEL_TYPE_STRING[size_t(model_type)], CIRCUIT_MODEL_TYPE_STRING[size_t(model_type)],
CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.circuit_model_type(circuit_model))]); CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))]);
} }
return circuit_model; return circuit_model;
@ -267,11 +267,11 @@ int link_pb_type_port_to_circuit_model_ports(const t_pb_type* cur_pb_type,
/* Initialize each port */ /* Initialize each port */
for (int iport = 0; iport < cur_pb_type->num_ports; iport++) { for (int iport = 0; iport < cur_pb_type->num_ports; iport++) {
cur_pb_type->ports[iport].circuit_model_port = CIRCUIT_PORT_OPEN_ID; cur_pb_type->ports[iport].circuit_model_port = CircuitPortId::INVALID();
} }
/* Return if SPICE_MODEL is NULL */ /* Return if SPICE_MODEL is NULL */
if (CIRCUIT_MODEL_OPEN_ID == circuit_model) { if (CircuitModelId::INVALID() == circuit_model) {
return 0; return 0;
} }
@ -290,11 +290,11 @@ int link_pb_type_port_to_circuit_model_ports(const t_pb_type* cur_pb_type,
* but each pb_type_port should be mapped to a spice_model_port * but each pb_type_port should be mapped to a spice_model_port
*/ */
for (int iport = 0; iport < cur_pb_type->num_ports; iport++) { for (int iport = 0; iport < cur_pb_type->num_ports; iport++) {
if (CIRCUIT_PORT_OPEN_ID == cur_pb_type->ports[iport].circuit_model_port) { if (CircuitPortId::INVALID() == cur_pb_type->ports[iport].circuit_model_port) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s, [LINE%d])Pb_type(%s) Port(%s) cannot find a corresponding port in SPICE model(%s)\n", "(File:%s, [LINE%d])Pb_type(%s) Port(%s) cannot find a corresponding port in SPICE model(%s)\n",
__FILE__, __LINE__, cur_pb_type->name, cur_pb_type->ports[iport].name, __FILE__, __LINE__, cur_pb_type->name, cur_pb_type->ports[iport].name,
circuit_lib.circuit_model_name(circuit_model).c_str()); circuit_lib.model_name(circuit_model).c_str());
exit(1); exit(1);
} }
} }
@ -319,7 +319,7 @@ void link_pb_type_interc_circuit_model_by_type(t_interconnect* cur_interc,
circuit_lib, circuit_lib,
model_type); model_type);
/* Check the circuit model, we should have one! */ /* Check the circuit model, we should have one! */
if (CIRCUIT_MODEL_OPEN_ID == cur_interc->circuit_model) { if (CircuitModelId::INVALID() == cur_interc->circuit_model) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s,LINE[%d]) Error in linking circuit model for interconnect(name %s)! Check [LINE%d] in architecture file)!\n", "(File:%s,LINE[%d]) Error in linking circuit model for interconnect(name %s)! Check [LINE%d] in architecture file)!\n",
__FILE__, __LINE__, __FILE__, __LINE__,
@ -415,8 +415,8 @@ void link_pb_types_circuit_model_rec(t_pb_type* cur_pb_type,
return; return;
} }
/* Let's find a matched circuit model!*/ /* Let's find a matched circuit model!*/
cur_pb_type->circuit_model = circuit_lib.circuit_model(cur_pb_type->spice_model_name); cur_pb_type->circuit_model = circuit_lib.model(cur_pb_type->spice_model_name);
if (CIRCUIT_MODEL_OPEN_ID == cur_pb_type->circuit_model) { if (CircuitModelId::INVALID() == cur_pb_type->circuit_model) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s,LINE[%d]) Fail to find a defined circuit model called %s, in pb_type(%s)!\n", "(File:%s,LINE[%d]) Fail to find a defined circuit model called %s, in pb_type(%s)!\n",
__FILE__, __LINE__, cur_pb_type->spice_model_name, cur_pb_type->name); __FILE__, __LINE__, cur_pb_type->spice_model_name, cur_pb_type->name);
@ -428,14 +428,14 @@ void link_pb_types_circuit_model_rec(t_pb_type* cur_pb_type,
} }
/* Otherwise, initialize it to be OPEN node */ /* Otherwise, initialize it to be OPEN node */
cur_pb_type->circuit_model = CIRCUIT_MODEL_OPEN_ID; cur_pb_type->circuit_model = CircuitModelId::INVALID();
/* Traversal the hierarchy*/ /* Traversal the hierarchy*/
for (int imode = 0; imode < cur_pb_type->num_modes; imode++) { for (int imode = 0; imode < cur_pb_type->num_modes; imode++) {
/* Task 1: Find the interconnections and match the spice_model */ /* Task 1: Find the interconnections and match the spice_model */
for (int jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { for (int jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) {
/* Initialize it to be OPEN node */ /* Initialize it to be OPEN node */
cur_pb_type->modes[imode].interconnect[jinterc].circuit_model = CIRCUIT_MODEL_OPEN_ID; cur_pb_type->modes[imode].interconnect[jinterc].circuit_model = CircuitModelId::INVALID();
link_pb_type_interc_circuit_model(&(cur_pb_type->modes[imode].interconnect[jinterc]), link_pb_type_interc_circuit_model(&(cur_pb_type->modes[imode].interconnect[jinterc]),
circuit_lib); circuit_lib);
} }
@ -453,12 +453,12 @@ size_t check_circuit_model_structure_match_switch_inf(const t_switch_inf& target
const CircuitLibrary& circuit_lib) { const CircuitLibrary& circuit_lib) {
size_t num_err = 0; size_t num_err = 0;
VTR_ASSERT_SAFE(CIRCUIT_MODEL_OPEN_ID != target_switch_inf.circuit_model); VTR_ASSERT_SAFE(CircuitModelId::INVALID() != target_switch_inf.circuit_model);
if (target_switch_inf.structure != circuit_lib.mux_structure(target_switch_inf.circuit_model)) { if (target_switch_inf.structure != circuit_lib.mux_structure(target_switch_inf.circuit_model)) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"(File:%s,[LINE%d]) Mismatch in MUX structure between circuit model(%s, %s) and switch_inf(%s, %s)!\n", "(File:%s,[LINE%d]) Mismatch in MUX structure between circuit model(%s, %s) and switch_inf(%s, %s)!\n",
__FILE__, __LINE__, __FILE__, __LINE__,
circuit_lib.circuit_model_name(target_switch_inf.circuit_model).c_str(), circuit_lib.model_name(target_switch_inf.circuit_model).c_str(),
CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[size_t(circuit_lib.mux_structure(target_switch_inf.circuit_model))], CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[size_t(circuit_lib.mux_structure(target_switch_inf.circuit_model))],
target_switch_inf.name, target_switch_inf.name,
CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[size_t(target_switch_inf.structure)]); CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[size_t(target_switch_inf.structure)]);
@ -494,7 +494,7 @@ void link_circuit_library_to_arch(t_arch* arch,
for (int i = 0; i < arch->num_cb_switch; i++) { for (int i = 0; i < arch->num_cb_switch; i++) {
arch->cb_switches[i].circuit_model = link_circuit_model_by_name_and_type(arch->cb_switches[i].spice_model_name, arch->cb_switches[i].circuit_model = link_circuit_model_by_name_and_type(arch->cb_switches[i].spice_model_name,
arch->spice->circuit_lib, SPICE_MODEL_MUX); arch->spice->circuit_lib, SPICE_MODEL_MUX);
if (CIRCUIT_MODEL_OPEN_ID == arch->cb_switches[i].circuit_model) { if (CircuitModelId::INVALID() == arch->cb_switches[i].circuit_model) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n",
__FILE__, __LINE__, arch->cb_switches[i].spice_model_name, arch->cb_switches[i].name); __FILE__, __LINE__, arch->cb_switches[i].spice_model_name, arch->cb_switches[i].name);
@ -517,7 +517,7 @@ void link_circuit_library_to_arch(t_arch* arch,
for (int i = 0; i < arch->num_switches; i++) { for (int i = 0; i < arch->num_switches; i++) {
arch->Switches[i].circuit_model = link_circuit_model_by_name_and_type(arch->Switches[i].spice_model_name, arch->Switches[i].circuit_model = link_circuit_model_by_name_and_type(arch->Switches[i].spice_model_name,
arch->spice->circuit_lib, SPICE_MODEL_MUX); arch->spice->circuit_lib, SPICE_MODEL_MUX);
if (CIRCUIT_MODEL_OPEN_ID == arch->Switches[i].circuit_model) { if (CircuitModelId::INVALID() == arch->Switches[i].circuit_model) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n",
__FILE__, __LINE__, arch->Switches[i].spice_model_name, arch->Switches[i].name); __FILE__, __LINE__, arch->Switches[i].spice_model_name, arch->Switches[i].name);
@ -533,7 +533,7 @@ void link_circuit_library_to_arch(t_arch* arch,
for (int i = 0; i < routing_arch->num_switch; i++) { for (int i = 0; i < routing_arch->num_switch; i++) {
switch_inf[i].circuit_model = link_circuit_model_by_name_and_type(switch_inf[i].spice_model_name, switch_inf[i].circuit_model = link_circuit_model_by_name_and_type(switch_inf[i].spice_model_name,
arch->spice->circuit_lib, SPICE_MODEL_MUX); arch->spice->circuit_lib, SPICE_MODEL_MUX);
if (CIRCUIT_MODEL_OPEN_ID == switch_inf[i].circuit_model) { if (CircuitModelId::INVALID() == switch_inf[i].circuit_model) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n",
__FILE__, __LINE__, switch_inf[i].spice_model_name, switch_inf[i].name); __FILE__, __LINE__, switch_inf[i].spice_model_name, switch_inf[i].name);
@ -548,7 +548,7 @@ void link_circuit_library_to_arch(t_arch* arch,
for (int i = 0; i < arch->num_segments; i++) { for (int i = 0; i < arch->num_segments; i++) {
arch->Segments[i].circuit_model = link_circuit_model_by_name_and_type(arch->Segments[i].spice_model_name, arch->Segments[i].circuit_model = link_circuit_model_by_name_and_type(arch->Segments[i].spice_model_name,
arch->spice->circuit_lib, SPICE_MODEL_CHAN_WIRE); arch->spice->circuit_lib, SPICE_MODEL_CHAN_WIRE);
if (CIRCUIT_MODEL_OPEN_ID == arch->Segments[i].circuit_model) { if (CircuitModelId::INVALID() == arch->Segments[i].circuit_model) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Segment(Length:%d) is undefined in circuit models!\n", "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Segment(Length:%d) is undefined in circuit models!\n",
__FILE__ ,__LINE__, __FILE__ ,__LINE__,
@ -563,7 +563,7 @@ void link_circuit_library_to_arch(t_arch* arch,
arch->Directs[i].circuit_model = link_circuit_model_by_name_and_type(arch->Directs[i].spice_model_name, arch->Directs[i].circuit_model = link_circuit_model_by_name_and_type(arch->Directs[i].spice_model_name,
arch->spice->circuit_lib, SPICE_MODEL_WIRE); arch->spice->circuit_lib, SPICE_MODEL_WIRE);
/* Check SPICE model type */ /* Check SPICE model type */
if (CIRCUIT_MODEL_OPEN_ID == arch->Directs[i].circuit_model) { if (CircuitModelId::INVALID() == arch->Directs[i].circuit_model) {
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s, LINE[%d])Invalid circuit model name(%s) of CLB to CLB Direct Connection (name=%s) is undefined in circuit models!\n", "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of CLB to CLB Direct Connection (name=%s) is undefined in circuit models!\n",
__FILE__ ,__LINE__, __FILE__ ,__LINE__,

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp
View File

@ -64,7 +64,7 @@ void generate_verilog_mux_branch_module(std::fstream& fp,
default: default:
vpr_printf(TIO_MESSAGE_ERROR, vpr_printf(TIO_MESSAGE_ERROR,
"(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n",
__FILE__, __LINE__, circuit_lib.circuit_model_name(circuit_model)); __FILE__, __LINE__, circuit_lib.model_name(circuit_model));
exit(1); exit(1);
} }