From a7ac1e498081f09e574097e6edba35a0305b3d4d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 19 Aug 2019 20:43:35 -0600 Subject: [PATCH] remame methods in circuit_library --- .../libarchfpga/SRC/check_circuit_library.cpp | 48 +- .../libarchfpga/SRC/check_circuit_library.h | 4 +- vpr7_x2p/libarchfpga/SRC/circuit_library.cpp | 1432 ++++++++--------- vpr7_x2p/libarchfpga/SRC/circuit_library.h | 378 +++-- .../libarchfpga/SRC/circuit_library_fwd.h | 21 + vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 44 +- vpr7_x2p/vpr/SRC/device/mux_graph.cpp | 6 +- vpr7_x2p/vpr/SRC/device/mux_utils.cpp | 8 +- .../fpga_x2p/base/link_arch_circuit_lib.cpp | 46 +- .../verilog/verilog_submodule_mux.cpp | 2 +- 10 files changed, 998 insertions(+), 991 deletions(-) create mode 100644 vpr7_x2p/libarchfpga/SRC/circuit_library_fwd.h diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp index 0b0f8fa69..2f51fa9bb 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.cpp @@ -58,16 +58,16 @@ static size_t check_circuit_library_unique_names(const CircuitLibrary& circuit_lib) { size_t num_err = 0; - for (size_t i = 0; i < circuit_lib.num_circuit_models(); ++i) { + for (size_t i = 0; i < circuit_lib.num_models(); ++i) { /* Skip for the last element, because the inner loop will access it */ - if (i == circuit_lib.num_circuit_models() - 1) { + if (i == circuit_lib.num_models() - 1) { continue; } /* Get the name of reference */ - const std::string& i_name = circuit_lib.circuit_model_name(CircuitModelId(i)); - for (size_t j = i + 1; j < circuit_lib.num_circuit_models(); ++j) { + const std::string& i_name = circuit_lib.model_name(CircuitModelId(i)); + for (size_t j = i + 1; j < circuit_lib.num_models(); ++j) { /* Compare the name of candidate */ - const std::string& j_name = circuit_lib.circuit_model_name(CircuitModelId(j)); + const std::string& j_name = circuit_lib.model_name(CircuitModelId(j)); /* Compare the name and skip for different names */ if (0 != i_name.compare(j_name)) { continue; @@ -92,24 +92,24 @@ static size_t check_circuit_library_unique_prefix(const CircuitLibrary& circuit_lib) { size_t num_err = 0; - for (size_t i = 0; i < circuit_lib.num_circuit_models(); ++i) { + for (size_t i = 0; i < circuit_lib.num_models(); ++i) { /* Skip for the last element, because the inner loop will access it */ - if (i == circuit_lib.num_circuit_models() - 1) { + if (i == circuit_lib.num_models() - 1) { continue; } /* Get the name of reference */ - const std::string& i_prefix = circuit_lib.circuit_model_prefix(CircuitModelId(i)); - for (size_t j = i + 1; j < circuit_lib.num_circuit_models(); ++j) { + const std::string& i_prefix = circuit_lib.model_prefix(CircuitModelId(i)); + for (size_t j = i + 1; j < circuit_lib.num_models(); ++j) { /* Compare the name of candidate */ - const std::string& j_prefix = circuit_lib.circuit_model_prefix(CircuitModelId(j)); + const std::string& j_prefix = circuit_lib.model_prefix(CircuitModelId(j)); /* Compare the name and skip for different prefix */ if (0 != i_prefix.compare(j_prefix)) { continue; } vpr_printf(TIO_MESSAGE_ERROR, "Circuit model(name=%s) and (name=%s) share the same prefix, which is invalid!\n", - circuit_lib.circuit_model_name(CircuitModelId(i)).c_str(), - circuit_lib.circuit_model_name(CircuitModelId(j)).c_str(), + circuit_lib.model_name(CircuitModelId(i)).c_str(), + circuit_lib.model_name(CircuitModelId(j)).c_str(), i_prefix.c_str()); /* Incremental the counter for errors */ num_err++; @@ -129,7 +129,7 @@ size_t check_circuit_model_required(const CircuitLibrary& circuit_lib, size_t num_err = 0; /* We must have an IOPAD*/ - if ( 0 == circuit_lib.circuit_models_by_type(circuit_model_type_to_check).size()) { + if ( 0 == circuit_lib.models_by_type(circuit_model_type_to_check).size()) { vpr_printf(TIO_MESSAGE_ERROR, "At least one %s circuit model is required!\n", CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type_to_check)]); @@ -153,8 +153,8 @@ size_t check_one_circuit_model_port_required(const CircuitLibrary& circuit_lib, if (0 == circuit_lib.ports_by_type(circuit_model, port_type).size()) { vpr_printf(TIO_MESSAGE_ERROR, "%s circuit model(name=%s) does not have %s port\n", - CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.circuit_model_type(circuit_model))], - circuit_lib.circuit_model_name(circuit_model).c_str(), + CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))], + circuit_lib.model_name(circuit_model).c_str(), CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type)]); /* Incremental the counter for errors */ num_err++; @@ -178,7 +178,7 @@ size_t check_one_circuit_model_port_size_required(const CircuitLibrary& circuit_ if (port_size_to_check != circuit_lib.port_size(circuit_model, circuit_port)) { vpr_printf(TIO_MESSAGE_ERROR, "Port of circuit model(name=%s) does not have a port(type=%s) of size=%d.\n", - circuit_lib.circuit_model_name(circuit_model).c_str(), + circuit_lib.model_name(circuit_model).c_str(), CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(circuit_model, circuit_port))], port_size_to_check); /* Incremental the counter for errors */ @@ -208,7 +208,7 @@ size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary& "Expect %d %s ports for a %s circuit model, but only have %d %s ports!\n", num_ports_to_check, CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)], - CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.circuit_model_type(circuit_model))], + CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))], CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)], ports.size()); num_err++; @@ -232,7 +232,7 @@ size_t check_circuit_model_port_required(const CircuitLibrary& circuit_lib, const std::vector& port_types_to_check) { size_t num_err = 0; - for (const auto& id : circuit_lib.circuit_models_by_type(circuit_model_type_to_check)) { + for (const auto& id : circuit_lib.models_by_type(circuit_model_type_to_check)) { num_err += check_one_circuit_model_port_required(circuit_lib, id, port_types_to_check); } @@ -248,7 +248,7 @@ size_t check_required_default_circuit_model(const CircuitLibrary& circuit_lib, const enum e_spice_model_type& circuit_model_type) { size_t num_err = 0; - if (CIRCUIT_MODEL_OPEN_ID == circuit_lib.default_circuit_model(circuit_model_type)) { + if (CircuitModelId::INVALID() == circuit_lib.default_model(circuit_model_type)) { vpr_printf(TIO_MESSAGE_ERROR, "A default circuit model for the type %s! Try to define it in your architecture file!\n", CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type)]); @@ -266,7 +266,7 @@ size_t check_ff_circuit_model_ports(const CircuitLibrary& circuit_lib, size_t num_err = 0; /* Check the type of circuit model */ - VTR_ASSERT(SPICE_MODEL_FF == circuit_lib.circuit_model_type(circuit_model)); + VTR_ASSERT(SPICE_MODEL_FF == circuit_lib.model_type(circuit_model)); /* Check if we have D, Set and Reset */ num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, SPICE_MODEL_PORT_INPUT, @@ -293,7 +293,7 @@ size_t check_scff_circuit_model_ports(const CircuitLibrary& circuit_lib, size_t num_err = 0; /* Check the type of circuit model */ - VTR_ASSERT(SPICE_MODEL_SCFF == circuit_lib.circuit_model_type(circuit_model)); + VTR_ASSERT(SPICE_MODEL_SCFF == circuit_lib.model_type(circuit_model)); /* Check if we have D, Set and Reset */ num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, @@ -322,7 +322,7 @@ size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib, size_t num_err = 0; /* Check the type of circuit model */ - VTR_ASSERT(SPICE_MODEL_SRAM == circuit_lib.circuit_model_type(circuit_model)); + VTR_ASSERT(SPICE_MODEL_SRAM == circuit_lib.model_type(circuit_model)); /* Check if we has 1 output with size 2 */ num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model, @@ -403,8 +403,8 @@ void check_circuit_library(const CircuitLibrary& circuit_lib) { num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_MUX, mux_port_types_required); /* 5. We must have at least one SRAM or SCFF */ - if ( ( 0 == circuit_lib.circuit_models_by_type(SPICE_MODEL_SRAM).size()) - && ( 0 == circuit_lib.circuit_models_by_type(SPICE_MODEL_SCFF).size()) ) { + if ( ( 0 == circuit_lib.models_by_type(SPICE_MODEL_SRAM).size()) + && ( 0 == circuit_lib.models_by_type(SPICE_MODEL_SCFF).size()) ) { vpr_printf(TIO_MESSAGE_ERROR, "At least one %s or %s circuit model is required!\n", CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_SRAM)], diff --git a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.h b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.h index f70133697..2d0bd3f03 100644 --- a/vpr7_x2p/libarchfpga/SRC/check_circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/check_circuit_library.h @@ -47,7 +47,9 @@ */ /* Header files should be included in a sequence */ /* Standard header files required go first */ -#include "circuit_library.h" +#include +#include "spice_types.h" +#include "circuit_library_fwd.h" /* Check points to make sure we have a valid circuit library */ size_t check_one_circuit_model_port_required(const CircuitLibrary& circuit_lib, diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp index 9689c8132..e39d81793 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.cpp @@ -55,20 +55,20 @@ CircuitLibrary::CircuitLibrary() { /************************************************************************ * Public Accessors : aggregates ***********************************************************************/ -CircuitLibrary::circuit_model_range CircuitLibrary::circuit_models() const { - return vtr::make_range(circuit_model_ids_.begin(), circuit_model_ids_.end()); +CircuitLibrary::model_range CircuitLibrary::models() const { + return vtr::make_range(model_ids_.begin(), model_ids_.end()); } -CircuitLibrary::circuit_port_range CircuitLibrary::ports(const CircuitModelId& circuit_model_id) const { - return vtr::make_range(port_ids_[circuit_model_id].begin(), port_ids_[circuit_model_id].end()); +CircuitLibrary::circuit_port_range CircuitLibrary::ports(const CircuitModelId& model_id) const { + return vtr::make_range(port_ids_[model_id].begin(), port_ids_[model_id].end()); } /* Find circuit models in the same type (defined by users) and return a list of ids */ -std::vector CircuitLibrary::circuit_models_by_type(const enum e_spice_model_type& type) const { +std::vector CircuitLibrary::models_by_type(const enum e_spice_model_type& type) const { std::vector type_ids; - for (auto id : circuit_models()) { + for (auto id : models()) { /* Skip unmatched types */ - if (type != circuit_model_type(id)) { + if (type != model_type(id)) { continue; } /* Matched type, update the vector */ @@ -78,12 +78,12 @@ std::vector CircuitLibrary::circuit_models_by_type(const enum e_ } /* Find the ports of a circuit model by a given type, return a list of qualified ports */ -std::vector CircuitLibrary::ports_by_type(const CircuitModelId& circuit_model_id, +std::vector CircuitLibrary::ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& type) const { std::vector port_ids; - for (const auto& port_id : ports(circuit_model_id)) { + for (const auto& port_id : ports(model_id)) { /* We skip unmatched ports */ - if ( type != port_type(circuit_model_id, port_id) ) { + if ( type != port_type(model_id, port_id) ) { continue; } port_ids.push_back(port_id); @@ -94,18 +94,18 @@ std::vector CircuitLibrary::ports_by_type(const CircuitModelId& c /* Find the ports of a circuit model by a given type, return a list of qualified ports * with an option to include/exclude global ports */ -std::vector CircuitLibrary::ports_by_type(const CircuitModelId& circuit_model_id, +std::vector CircuitLibrary::ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& type, const bool& include_global_port) const { std::vector port_ids; - for (const auto& port_id : ports(circuit_model_id)) { + for (const auto& port_id : ports(model_id)) { /* We skip unmatched ports */ - if ( type != port_type(circuit_model_id, port_id) ) { + if ( type != port_type(model_id, port_id) ) { continue; } /* We skip global ports if specified */ if ( (false == include_global_port) - && (true == port_is_global(circuit_model_id, port_id)) ) { + && (true == port_is_global(model_id, port_id)) ) { continue; } port_ids.push_back(port_id); @@ -117,11 +117,11 @@ std::vector CircuitLibrary::ports_by_type(const CircuitModelId& c /* Create a vector for all the ports whose directionality is input * This includes all the ports other than whose types are OUPUT or INOUT */ -std::vector CircuitLibrary::input_ports(const CircuitModelId& circuit_model_id) const { +std::vector CircuitLibrary::input_ports(const CircuitModelId& model_id) const { std::vector input_ports; - for (const auto& port_id : ports(circuit_model_id)) { + for (const auto& port_id : ports(model_id)) { /* We skip output ports */ - if ( false == is_input_port(circuit_model_id, port_id) ) { + if ( false == is_input_port(model_id, port_id) ) { continue; } input_ports.push_back(port_id); @@ -132,11 +132,11 @@ std::vector CircuitLibrary::input_ports(const CircuitModelId& cir /* Create a vector for all the ports whose directionality is output * This includes all the ports whose types are OUPUT or INOUT */ -std::vector CircuitLibrary::output_ports(const CircuitModelId& circuit_model_id) const { +std::vector CircuitLibrary::output_ports(const CircuitModelId& model_id) const { std::vector output_ports; - for (const auto& port_id : ports(circuit_model_id)) { + for (const auto& port_id : ports(model_id)) { /* We skip input ports */ - if ( false == is_output_port(circuit_model_id, port_id) ) { + if ( false == is_output_port(model_id, port_id) ) { continue; } output_ports.push_back(port_id); @@ -147,8 +147,8 @@ std::vector CircuitLibrary::output_ports(const CircuitModelId& ci /* Create a vector for the pin indices, which is bounded by the size of a port * Start from 0 and end to port_size - 1 */ -std::vector CircuitLibrary::pins(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { - std::vector pin_range(port_size(circuit_model_id, circuit_port_id)); +std::vector CircuitLibrary::pins(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { + std::vector pin_range(port_size(model_id, circuit_port_id)); /* Create a vector, with sequentially increasing numbers */ std::iota(pin_range.begin(), pin_range.end(), 0); return pin_range; @@ -159,101 +159,101 @@ std::vector CircuitLibrary::pins(const CircuitModelId& circuit_model_id, * Public Accessors : Basic data query on Circuit Models ***********************************************************************/ /* Get the number of circuit models */ -size_t CircuitLibrary::num_circuit_models() const { - return circuit_model_ids_.size(); +size_t CircuitLibrary::num_models() const { + return model_ids_.size(); } /* Access the type of a circuit model */ -enum e_spice_model_type CircuitLibrary::circuit_model_type(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return circuit_model_types_[circuit_model_id]; +enum e_spice_model_type CircuitLibrary::model_type(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return model_types_[model_id]; } /* Access the name of a circuit model */ -std::string CircuitLibrary::circuit_model_name(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return circuit_model_names_[circuit_model_id]; +std::string CircuitLibrary::model_name(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return model_names_[model_id]; } /* Access the prefix of a circuit model */ -std::string CircuitLibrary::circuit_model_prefix(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return circuit_model_prefix_[circuit_model_id]; +std::string CircuitLibrary::model_prefix(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return model_prefix_[model_id]; } /* Access the path + file of user-defined verilog netlist of a circuit model */ -std::string CircuitLibrary::circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return circuit_model_verilog_netlists_[circuit_model_id]; +std::string CircuitLibrary::model_verilog_netlist(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return model_verilog_netlists_[model_id]; } /* Access the path + file of user-defined spice netlist of a circuit model */ -std::string CircuitLibrary::circuit_model_spice_netlist(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return circuit_model_spice_netlists_[circuit_model_id]; +std::string CircuitLibrary::model_spice_netlist(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return model_spice_netlists_[model_id]; } /* Access the is_default flag (check if this is the default circuit model in the type) of a circuit model */ -bool CircuitLibrary::circuit_model_is_default(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return circuit_model_is_default_[circuit_model_id]; +bool CircuitLibrary::model_is_default(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return model_is_default_[model_id]; } /* Access the dump_structural_verilog flag of a circuit model */ -bool CircuitLibrary::dump_structural_verilog(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return dump_structural_verilog_[circuit_model_id]; +bool CircuitLibrary::dump_structural_verilog(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return dump_structural_verilog_[model_id]; } /* Access the dump_explicit_port_map flag of a circuit model */ -bool CircuitLibrary::dump_explicit_port_map(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return dump_explicit_port_map_[circuit_model_id]; +bool CircuitLibrary::dump_explicit_port_map(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return dump_explicit_port_map_[model_id]; } /* Access the design technology type of a circuit model */ -enum e_spice_model_design_tech CircuitLibrary::design_tech_type(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return design_tech_types_[circuit_model_id]; +enum e_spice_model_design_tech CircuitLibrary::design_tech_type(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return design_tech_types_[model_id]; } /* Access the is_power_gated flag of a circuit model */ -bool CircuitLibrary::is_power_gated(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return is_power_gated_[circuit_model_id]; +bool CircuitLibrary::is_power_gated(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return is_power_gated_[model_id]; } /* Return a flag showing if inputs are buffered for a circuit model */ -bool CircuitLibrary::is_input_buffered(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return buffer_existence_[circuit_model_id][INPUT]; +bool CircuitLibrary::is_input_buffered(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return buffer_existence_[model_id][INPUT]; } /* Return a flag showing if outputs are buffered for a circuit model */ -bool CircuitLibrary::is_output_buffered(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return buffer_existence_[circuit_model_id][OUTPUT]; +bool CircuitLibrary::is_output_buffered(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return buffer_existence_[model_id][OUTPUT]; } /* Return a flag showing if intermediate stages of a LUT are buffered for a circuit model */ -bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* validate the circuit model type is LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); - return buffer_existence_[circuit_model_id][LUT_INTER_BUFFER]; + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + return buffer_existence_[model_id][LUT_INTER_BUFFER]; } /* Find the type of pass-gate logic for a circuit model (recursive function) @@ -261,68 +261,68 @@ bool CircuitLibrary::is_lut_intermediate_buffered(const CircuitModelId& circuit_ * 1. this is a pass-gate circuit model, just find the data and return * 2. this circuit model includes a pass-gate, find the link to pass-gate circuit model and go recursively */ -enum e_spice_model_pass_gate_logic_type CircuitLibrary::pass_gate_logic_type(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +enum e_spice_model_pass_gate_logic_type CircuitLibrary::pass_gate_logic_type(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Return the data if this is a pass-gate circuit model */ - if (SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)) { - return pass_gate_logic_types_[circuit_model_id]; + if (SPICE_MODEL_PASSGATE == model_type(model_id)) { + return pass_gate_logic_types_[model_id]; } /* Otherwise, we need to make sure this circuit model contains a pass-gate */ - CircuitModelId pgl_model_id = pass_gate_logic_circuit_model_ids_[circuit_model_id]; + CircuitModelId pgl_model_id = pass_gate_logic_model_ids_[model_id]; VTR_ASSERT( CircuitModelId::INVALID() != pgl_model_id ); return pass_gate_logic_type(pgl_model_id); } /* Return the multiplex structure of a circuit model */ -enum e_spice_model_structure CircuitLibrary::mux_structure(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +enum e_spice_model_structure CircuitLibrary::mux_structure(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* validate the circuit model type is MUX */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); - return mux_structure_[circuit_model_id]; + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); + return mux_structure_[model_id]; } -size_t CircuitLibrary::mux_num_levels(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +size_t CircuitLibrary::mux_num_levels(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* validate the circuit model type is MUX */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); - return mux_num_levels_[circuit_model_id]; + return mux_num_levels_[model_id]; } /* Return if additional constant inputs are required for a circuit model * Only applicable for MUX circuit model */ -bool CircuitLibrary::mux_add_const_input(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +bool CircuitLibrary::mux_add_const_input(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* validate the circuit model type is MUX */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); /* A -1 value for the const values means there is no const inputs */ - return ( size_t(-1) != mux_const_input_values_[circuit_model_id] ); + return ( size_t(-1) != mux_const_input_values_[model_id] ); } /* Return if additional constant inputs are required for a circuit model * Only applicable for MUX circuit model */ -size_t CircuitLibrary::mux_const_input_value(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +size_t CircuitLibrary::mux_const_input_value(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* validate the circuit model type is MUX */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); /* A -1 value for the const values means there is no const inputs */ /* A 0 value for the const values means it is logic 0 */ /* A 1 value for the const values means it is logic 1 */ - return mux_const_input_values_[circuit_model_id]; + return mux_const_input_values_[model_id]; } /************************************************************************ @@ -330,32 +330,32 @@ size_t CircuitLibrary::mux_const_input_value(const CircuitModelId& circuit_model ***********************************************************************/ /* identify if this port is an input port */ -bool CircuitLibrary::is_input_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { - /* validate the circuit_model_id and circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); +bool CircuitLibrary::is_input_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { + /* validate the model_id and circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ - return ( (SPICE_MODEL_PORT_OUTPUT != port_type(circuit_model_id, circuit_port_id)) - && (SPICE_MODEL_PORT_INOUT != port_type(circuit_model_id, circuit_port_id)) ); + return ( (SPICE_MODEL_PORT_OUTPUT != port_type(model_id, circuit_port_id)) + && (SPICE_MODEL_PORT_INOUT != port_type(model_id, circuit_port_id)) ); } /* identify if this port is an output port */ -bool CircuitLibrary::is_output_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { - /* validate the circuit_model_id and circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); +bool CircuitLibrary::is_output_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { + /* validate the model_id and circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); /* Only SPICE_MODEL_OUTPUT AND INOUT are considered as outputs */ - return ( (SPICE_MODEL_PORT_OUTPUT == port_type(circuit_model_id, circuit_port_id)) - || (SPICE_MODEL_PORT_INOUT == port_type(circuit_model_id, circuit_port_id)) ); + return ( (SPICE_MODEL_PORT_OUTPUT == port_type(model_id, circuit_port_id)) + || (SPICE_MODEL_PORT_INOUT == port_type(model_id, circuit_port_id)) ); } /* Given a name and return the port id */ -CircuitPortId CircuitLibrary::port(const CircuitModelId& circuit_model_id, const std::string& name) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +CircuitPortId CircuitLibrary::port(const CircuitModelId& model_id, const std::string& name) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Walk through the ports and try to find a matched name */ - CircuitPortId ret = CIRCUIT_PORT_OPEN_ID; + CircuitPortId ret = CircuitPortId::INVALID(); size_t num_found = 0; - for (auto port_id : ports(circuit_model_id)) { - if (0 != name.compare(port_prefix(circuit_model_id, port_id))) { + for (auto port_id : ports(model_id)) { + if (0 != name.compare(port_prefix(model_id, port_id))) { continue; /* Not the one, go to the next*/ } ret = port_id; /* Find one */ @@ -367,119 +367,119 @@ CircuitPortId CircuitLibrary::port(const CircuitModelId& circuit_model_id, const } /* Access the type of a port of a circuit model */ -size_t CircuitLibrary::num_ports(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return port_ids_[circuit_model_id].size(); +size_t CircuitLibrary::num_ports(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return port_ids_[model_id].size(); } /* Access the type of a port of a circuit model * with an option to include/exclude global ports * when counting */ -size_t CircuitLibrary::num_ports_by_type(const CircuitModelId& circuit_model_id, +size_t CircuitLibrary::num_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return ports_by_type(circuit_model_id, port_type, include_global_port).size(); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return ports_by_type(model_id, port_type, include_global_port).size(); } /* Access the type of a port of a circuit model */ -enum e_spice_model_port_type CircuitLibrary::port_type(const CircuitModelId& circuit_model_id, +enum e_spice_model_port_type CircuitLibrary::port_type(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_types_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_types_[model_id][circuit_port_id]; } /* Access the type of a port of a circuit model */ -size_t CircuitLibrary::port_size(const CircuitModelId& circuit_model_id, +size_t CircuitLibrary::port_size(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_sizes_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_sizes_[model_id][circuit_port_id]; } /* Access the prefix of a port of a circuit model */ -std::string CircuitLibrary::port_prefix(const CircuitModelId& circuit_model_id, +std::string CircuitLibrary::port_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_prefix_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_prefix_[model_id][circuit_port_id]; } /* Access the lib_name of a port of a circuit model */ -std::string CircuitLibrary::port_lib_name(const CircuitModelId& circuit_model_id, +std::string CircuitLibrary::port_lib_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_lib_names_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_lib_names_[model_id][circuit_port_id]; } /* Access the inv_prefix of a port of a circuit model */ -std::string CircuitLibrary::port_inv_prefix(const CircuitModelId& circuit_model_id, +std::string CircuitLibrary::port_inv_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_inv_prefix_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_inv_prefix_[model_id][circuit_port_id]; } /* Return the default value of a port of a circuit model */ -size_t CircuitLibrary::port_default_value(const CircuitModelId& circuit_model_id, +size_t CircuitLibrary::port_default_value(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_default_values_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_default_values_[model_id][circuit_port_id]; } /* Return a flag if the port is used in mode-selection purpuse of a circuit model */ -bool CircuitLibrary::port_is_mode_select(const CircuitModelId& circuit_model_id, +bool CircuitLibrary::port_is_mode_select(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_is_mode_select_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_is_mode_select_[model_id][circuit_port_id]; } /* Return a flag if the port is a global one of a circuit model */ -bool CircuitLibrary::port_is_global(const CircuitModelId& circuit_model_id, +bool CircuitLibrary::port_is_global(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_is_global_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_is_global_[model_id][circuit_port_id]; } /* Return a flag if the port does a reset functionality in a circuit model */ -bool CircuitLibrary::port_is_reset(const CircuitModelId& circuit_model_id, +bool CircuitLibrary::port_is_reset(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_is_reset_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_is_reset_[model_id][circuit_port_id]; } /* Return a flag if the port does a set functionality in a circuit model */ -bool CircuitLibrary::port_is_set(const CircuitModelId& circuit_model_id, +bool CircuitLibrary::port_is_set(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_is_set_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_is_set_[model_id][circuit_port_id]; } /* Return a flag if the port enables a configuration in a circuit model */ -bool CircuitLibrary::port_is_config_enable(const CircuitModelId& circuit_model_id, +bool CircuitLibrary::port_is_config_enable(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_is_config_enable_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_is_config_enable_[model_id][circuit_port_id]; } /* Return a flag if the port is used during programming a FPGA in a circuit model */ -bool CircuitLibrary::port_is_prog(const CircuitModelId& circuit_model_id, +bool CircuitLibrary::port_is_prog(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return port_is_prog_[circuit_model_id][circuit_port_id]; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return port_is_prog_[model_id][circuit_port_id]; } @@ -487,17 +487,17 @@ bool CircuitLibrary::port_is_prog(const CircuitModelId& circuit_model_id, * Public Accessors : Methods to find circuit model ***********************************************************************/ /* Find a circuit model by a given name and return its id */ -CircuitModelId CircuitLibrary::circuit_model(const char* name) const { +CircuitModelId CircuitLibrary::model(const char* name) const { std::string name_str(name); - return circuit_model(name_str); + return model(name_str); } /* Find a circuit model by a given name and return its id */ -CircuitModelId CircuitLibrary::circuit_model(const std::string& name) const { - CircuitModelId ret = CIRCUIT_MODEL_OPEN_ID; +CircuitModelId CircuitLibrary::model(const std::string& name) const { + CircuitModelId ret = CircuitModelId::INVALID(); size_t num_found = 0; - for (circuit_model_string_iterator it = circuit_model_names_.begin(); - it != circuit_model_names_.end(); + for (model_string_iterator it = model_names_.begin(); + it != model_names_.end(); it++) { /* Bypass unmatched names */ if ( 0 != name.compare(*it) ) { @@ -506,7 +506,7 @@ CircuitModelId CircuitLibrary::circuit_model(const std::string& name) const { /* Find one and record it * FIXME: I feel that we may have a better way in getting the CircuitModelId */ - ret = CircuitModelId(it - circuit_model_names_.begin()); + ret = CircuitModelId(it - model_names_.begin()); num_found++; } VTR_ASSERT((0 == num_found) || (1 == num_found)); @@ -514,10 +514,10 @@ CircuitModelId CircuitLibrary::circuit_model(const std::string& name) const { } /* Get the CircuitModelId of a default circuit model with a given type */ -CircuitModelId CircuitLibrary::default_circuit_model(const enum e_spice_model_type& type) const { +CircuitModelId CircuitLibrary::default_model(const enum e_spice_model_type& type) const { /* Default circuit model id is the first element by type in the fast look-up */ - CircuitModelId default_id = circuit_model_lookup_[size_t(type)].front(); - VTR_ASSERT(true == circuit_model_is_default(default_id)); + CircuitModelId default_id = model_lookup_[size_t(type)].front(); + VTR_ASSERT(true == model_is_default(default_id)); return default_id; } @@ -525,43 +525,43 @@ CircuitModelId CircuitLibrary::default_circuit_model(const enum e_spice_model_ty * Public Accessors: Timing graph ***********************************************************************/ /* Given the source and sink port information, find the edge connecting the two ports */ -CircuitEdgeId CircuitLibrary::edge(const CircuitModelId& circuit_model_id, +CircuitEdgeId CircuitLibrary::edge(const CircuitModelId& model_id, const CircuitPortId& from_port, const size_t from_pin, const CircuitPortId& to_port, const size_t to_pin) { /* validate the circuit_pin_id */ - VTR_ASSERT(valid_circuit_pin_id(circuit_model_id, from_port, from_pin)); - VTR_ASSERT(valid_circuit_pin_id(circuit_model_id, to_port, to_pin)); + VTR_ASSERT(valid_circuit_pin_id(model_id, from_port, from_pin)); + VTR_ASSERT(valid_circuit_pin_id(model_id, to_port, to_pin)); /* Walk through the edge list until we find the one */ - for (auto edge : edge_ids_[circuit_model_id]) { - if ( (from_port == edge_src_port_ids_[circuit_model_id][edge]) - && (from_pin == edge_src_pin_ids_[circuit_model_id][edge]) - && (to_port == edge_sink_port_ids_[circuit_model_id][edge]) - && (to_pin == edge_sink_pin_ids_[circuit_model_id][edge]) ) { + for (auto edge : edge_ids_[model_id]) { + if ( (from_port == edge_src_port_ids_[model_id][edge]) + && (from_pin == edge_src_pin_ids_[model_id][edge]) + && (to_port == edge_sink_port_ids_[model_id][edge]) + && (to_pin == edge_sink_pin_ids_[model_id][edge]) ) { return edge; } } /* Reach here it means we find nothing! */ - return CIRCUIT_EDGE_OPEN_ID; + return CircuitEdgeId::INVALID(); } /************************************************************************ * Public Mutators ***********************************************************************/ /* Add a circuit model to the library, and return it Id */ -CircuitModelId CircuitLibrary::add_circuit_model() { +CircuitModelId CircuitLibrary::add_model() { /* Create a new id*/ - CircuitModelId circuit_model_id = CircuitModelId(circuit_model_ids_.size()); + CircuitModelId model_id = CircuitModelId(model_ids_.size()); /* Update the id list */ - circuit_model_ids_.push_back(circuit_model_id); + model_ids_.push_back(model_id); /* Initialize other attributes */ /* Fundamental information */ - circuit_model_types_.push_back(NUM_CIRCUIT_MODEL_TYPES); - circuit_model_names_.emplace_back(); - circuit_model_prefix_.emplace_back(); - circuit_model_verilog_netlists_.emplace_back(); - circuit_model_spice_netlists_.emplace_back(); - circuit_model_is_default_.push_back(false); + model_types_.push_back(NUM_CIRCUIT_MODEL_TYPES); + model_names_.emplace_back(); + model_prefix_.emplace_back(); + model_verilog_netlists_.emplace_back(); + model_spice_netlists_.emplace_back(); + model_is_default_.push_back(false); /* Verilog generator options */ dump_structural_verilog_.push_back(false); @@ -573,13 +573,13 @@ CircuitModelId CircuitLibrary::add_circuit_model() { /* Buffer existence */ buffer_existence_.emplace_back(); - buffer_circuit_model_names_.emplace_back(); - buffer_circuit_model_ids_.emplace_back(); + buffer_model_names_.emplace_back(); + buffer_model_ids_.emplace_back(); buffer_location_maps_.emplace_back(); /* Pass-gate-related parameters */ - pass_gate_logic_circuit_model_names_.emplace_back(); - pass_gate_logic_circuit_model_ids_.emplace_back(); + pass_gate_logic_model_names_.emplace_back(); + pass_gate_logic_model_ids_.emplace_back(); /* Port information */ port_ids_.emplace_back(); @@ -595,10 +595,10 @@ CircuitModelId CircuitLibrary::add_circuit_model() { port_is_set_.emplace_back(); port_is_config_enable_.emplace_back(); port_is_prog_.emplace_back(); - port_circuit_model_names_.emplace_back(); - port_circuit_model_ids_.emplace_back(); - port_inv_circuit_model_names_.emplace_back(); - port_inv_circuit_model_ids_.emplace_back(); + port_model_names_.emplace_back(); + port_model_ids_.emplace_back(); + port_inv_model_names_.emplace_back(); + port_inv_model_ids_.emplace_back(); port_tri_state_maps_.emplace_back(); port_lut_frac_level_.emplace_back(); port_lut_output_masks_.emplace_back(); @@ -654,409 +654,409 @@ CircuitModelId CircuitLibrary::add_circuit_model() { wire_num_levels_.push_back(-1); /* Update circuit port fast look-up */ - circuit_model_port_lookup_.emplace_back(); + model_port_lookup_.emplace_back(); /* Invalidate fast look-up*/ - invalidate_circuit_model_lookup(); + invalidate_model_lookup(); - return circuit_model_id; + return model_id; } /* Set the type of a Circuit Model */ -void CircuitLibrary::set_circuit_model_type(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_model_type(const CircuitModelId& model_id, const enum e_spice_model_type& type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_types_[circuit_model_id] = type; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_types_[model_id] = type; /* Build the fast look-up for circuit models */ - build_circuit_model_lookup(); + build_model_lookup(); return; } /* Set the name of a Circuit Model */ -void CircuitLibrary::set_circuit_model_name(const CircuitModelId& circuit_model_id, const std::string& name) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_names_[circuit_model_id] = name; +void CircuitLibrary::set_model_name(const CircuitModelId& model_id, const std::string& name) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_names_[model_id] = name; return; } /* Set the prefix of a Circuit Model */ -void CircuitLibrary::set_circuit_model_prefix(const CircuitModelId& circuit_model_id, const std::string& prefix) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_prefix_[circuit_model_id] = prefix; +void CircuitLibrary::set_model_prefix(const CircuitModelId& model_id, const std::string& prefix) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_prefix_[model_id] = prefix; return; } /* Set the verilog_netlist of a Circuit Model */ -void CircuitLibrary::set_circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id, const std::string& verilog_netlist) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_verilog_netlists_[circuit_model_id] = verilog_netlist; +void CircuitLibrary::set_model_verilog_netlist(const CircuitModelId& model_id, const std::string& verilog_netlist) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_verilog_netlists_[model_id] = verilog_netlist; return; } /* Set the spice_netlist of a Circuit Model */ -void CircuitLibrary::set_circuit_model_spice_netlist(const CircuitModelId& circuit_model_id, const std::string& spice_netlist) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_spice_netlists_[circuit_model_id] = spice_netlist; +void CircuitLibrary::set_model_spice_netlist(const CircuitModelId& model_id, const std::string& spice_netlist) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_spice_netlists_[model_id] = spice_netlist; return; } /* Set the is_default of a Circuit Model */ -void CircuitLibrary::set_circuit_model_is_default(const CircuitModelId& circuit_model_id, const bool& is_default) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_is_default_[circuit_model_id] = is_default; +void CircuitLibrary::set_model_is_default(const CircuitModelId& model_id, const bool& is_default) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_is_default_[model_id] = is_default; return; } /* Set the dump_structural_verilog of a Circuit Model */ -void CircuitLibrary::set_circuit_model_dump_structural_verilog(const CircuitModelId& circuit_model_id, const bool& dump_structural_verilog) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - dump_structural_verilog_[circuit_model_id] = dump_structural_verilog; +void CircuitLibrary::set_model_dump_structural_verilog(const CircuitModelId& model_id, const bool& dump_structural_verilog) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + dump_structural_verilog_[model_id] = dump_structural_verilog; return; } /* Set the dump_explicit_port_map of a Circuit Model */ -void CircuitLibrary::set_circuit_model_dump_explicit_port_map(const CircuitModelId& circuit_model_id, const bool& dump_explicit_port_map) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - dump_explicit_port_map_[circuit_model_id] = dump_explicit_port_map; +void CircuitLibrary::set_model_dump_explicit_port_map(const CircuitModelId& model_id, const bool& dump_explicit_port_map) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + dump_explicit_port_map_[model_id] = dump_explicit_port_map; return; } /* Set the type of design technology of a Circuit Model */ -void CircuitLibrary::set_circuit_model_design_tech_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_design_tech& design_tech_type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - design_tech_types_[circuit_model_id] = design_tech_type; +void CircuitLibrary::set_model_design_tech_type(const CircuitModelId& model_id, const enum e_spice_model_design_tech& design_tech_type) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + design_tech_types_[model_id] = design_tech_type; return; } /* Set the power-gated flag of a Circuit Model */ -void CircuitLibrary::set_circuit_model_is_power_gated(const CircuitModelId& circuit_model_id, const bool& is_power_gated) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - is_power_gated_[circuit_model_id] = is_power_gated; +void CircuitLibrary::set_model_is_power_gated(const CircuitModelId& model_id, const bool& is_power_gated) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + is_power_gated_[model_id] = is_power_gated; return; } /* Set input buffer information for the circuit model */ -void CircuitLibrary::set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name) { +void CircuitLibrary::set_model_input_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name) { /* Just call the base function and give the proper type */ - set_circuit_model_buffer(circuit_model_id, INPUT, existence, circuit_model_name); + set_model_buffer(model_id, INPUT, existence, model_name); return; } /* Set output buffer information for the circuit model */ -void CircuitLibrary::set_circuit_model_output_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name) { +void CircuitLibrary::set_model_output_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name) { /* Just call the base function and give the proper type */ - set_circuit_model_buffer(circuit_model_id, OUTPUT, existence, circuit_model_name); + set_model_buffer(model_id, OUTPUT, existence, model_name); return; } /* Set input buffer information for the circuit model, only applicable to LUTs! */ -void CircuitLibrary::set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::set_model_lut_input_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Make sure the circuit model is a LUT! */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + VTR_ASSERT(SPICE_MODEL_LUT == model_types_[model_id]); /* Just call the base function and give the proper type */ - set_circuit_model_buffer(circuit_model_id, LUT_INPUT_BUFFER, existence, circuit_model_name); + set_model_buffer(model_id, LUT_INPUT_BUFFER, existence, model_name); return; } /* Set input inverter information for the circuit model, only applicable to LUTs! */ -void CircuitLibrary::set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::set_model_lut_input_inverter(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Make sure the circuit model is a LUT! */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + VTR_ASSERT(SPICE_MODEL_LUT == model_types_[model_id]); /* Just call the base function and give the proper type */ - set_circuit_model_buffer(circuit_model_id, LUT_INPUT_INVERTER, existence, circuit_model_name); + set_model_buffer(model_id, LUT_INPUT_INVERTER, existence, model_name); return; } /* Set intermediate buffer information for the circuit model, only applicable to LUTs! */ -void CircuitLibrary::set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::set_model_lut_intermediate_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Make sure the circuit model is a LUT! */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_types_[circuit_model_id]); + VTR_ASSERT(SPICE_MODEL_LUT == model_types_[model_id]); /* Just call the base function and give the proper type */ - set_circuit_model_buffer(circuit_model_id, LUT_INTER_BUFFER, existence, circuit_model_name); + set_model_buffer(model_id, LUT_INTER_BUFFER, existence, model_name); return; } -void CircuitLibrary::set_circuit_model_lut_intermediate_buffer_location_map(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_model_lut_intermediate_buffer_location_map(const CircuitModelId& model_id, const std::string& location_map) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - buffer_location_maps_[circuit_model_id][LUT_INTER_BUFFER] = location_map; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + buffer_location_maps_[model_id][LUT_INTER_BUFFER] = location_map; return; } /* Set pass-gate logic information of a circuit model */ -void CircuitLibrary::set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - pass_gate_logic_circuit_model_names_[circuit_model_id] = circuit_model_name; +void CircuitLibrary::set_model_pass_gate_logic(const CircuitModelId& model_id, const std::string& model_name) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + pass_gate_logic_model_names_[model_id] = model_name; return; } /* Add a port to a circuit model */ -CircuitPortId CircuitLibrary::add_circuit_model_port(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Create a port id */ - CircuitPortId circuit_port_id = CircuitPortId(port_ids_[circuit_model_id].size()); + CircuitPortId circuit_port_id = CircuitPortId(port_ids_[model_id].size()); /* Update the id list */ - port_ids_[circuit_model_id].push_back(circuit_port_id); + port_ids_[model_id].push_back(circuit_port_id); /* Initialize other attributes */ - port_types_[circuit_model_id].push_back(NUM_CIRCUIT_MODEL_PORT_TYPES); - port_sizes_[circuit_model_id].push_back(-1); - port_prefix_[circuit_model_id].emplace_back(); - port_lib_names_[circuit_model_id].emplace_back(); - port_inv_prefix_[circuit_model_id].emplace_back(); - port_default_values_[circuit_model_id].push_back(-1); - port_is_mode_select_[circuit_model_id].push_back(false); - port_is_global_[circuit_model_id].push_back(false); - port_is_reset_[circuit_model_id].push_back(false); - port_is_set_[circuit_model_id].push_back(false); - port_is_config_enable_[circuit_model_id].push_back(false); - port_is_prog_[circuit_model_id].push_back(false); - port_circuit_model_names_[circuit_model_id].emplace_back(); - port_circuit_model_ids_[circuit_model_id].push_back(CIRCUIT_MODEL_OPEN_ID); - port_inv_circuit_model_names_[circuit_model_id].emplace_back(); - port_inv_circuit_model_ids_[circuit_model_id].push_back(CIRCUIT_MODEL_OPEN_ID); - port_tri_state_maps_[circuit_model_id].emplace_back(); - port_lut_frac_level_[circuit_model_id].push_back(-1); - port_lut_output_masks_[circuit_model_id].emplace_back(); - port_sram_orgz_[circuit_model_id].push_back(NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES); + port_types_[model_id].push_back(NUM_CIRCUIT_MODEL_PORT_TYPES); + port_sizes_[model_id].push_back(-1); + port_prefix_[model_id].emplace_back(); + port_lib_names_[model_id].emplace_back(); + port_inv_prefix_[model_id].emplace_back(); + port_default_values_[model_id].push_back(-1); + port_is_mode_select_[model_id].push_back(false); + port_is_global_[model_id].push_back(false); + port_is_reset_[model_id].push_back(false); + port_is_set_[model_id].push_back(false); + port_is_config_enable_[model_id].push_back(false); + port_is_prog_[model_id].push_back(false); + port_model_names_[model_id].emplace_back(); + port_model_ids_[model_id].push_back(CircuitModelId::INVALID()); + port_inv_model_names_[model_id].emplace_back(); + port_inv_model_ids_[model_id].push_back(CircuitModelId::INVALID()); + port_tri_state_maps_[model_id].emplace_back(); + port_lut_frac_level_[model_id].push_back(-1); + port_lut_output_masks_[model_id].emplace_back(); + port_sram_orgz_[model_id].push_back(NUM_CIRCUIT_MODEL_SRAM_ORGZ_TYPES); /* For timing graphs */ - port_in_edge_ids_[circuit_model_id].emplace_back(); - port_out_edge_ids_[circuit_model_id].emplace_back(); + port_in_edge_ids_[model_id].emplace_back(); + port_out_edge_ids_[model_id].emplace_back(); return circuit_port_id; } /* Set the type for a port of a circuit model */ -void CircuitLibrary::set_port_type(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_type(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const enum e_spice_model_port_type& port_type) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_types_[circuit_model_id][circuit_port_id] = port_type; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_types_[model_id][circuit_port_id] = port_type; /* Build the fast look-up for circuit model ports */ - build_circuit_model_port_lookup(circuit_model_id); + build_model_port_lookup(model_id); return; } /* Set the size for a port of a circuit model */ -void CircuitLibrary::set_port_size(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_size(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& port_size) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_sizes_[circuit_model_id][circuit_port_id] = port_size; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_sizes_[model_id][circuit_port_id] = port_size; return; } /* Set the prefix for a port of a circuit model */ -void CircuitLibrary::set_port_prefix(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& port_prefix) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_prefix_[circuit_model_id][circuit_port_id] = port_prefix; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_prefix_[model_id][circuit_port_id] = port_prefix; return; } /* Set the lib_name for a port of a circuit model */ -void CircuitLibrary::set_port_lib_name(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_lib_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& lib_name) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_lib_names_[circuit_model_id][circuit_port_id] = lib_name; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_lib_names_[model_id][circuit_port_id] = lib_name; return; } /* Set the inv_prefix for a port of a circuit model */ -void CircuitLibrary::set_port_inv_prefix(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_inv_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& inv_prefix) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_inv_prefix_[circuit_model_id][circuit_port_id] = inv_prefix; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_inv_prefix_[model_id][circuit_port_id] = inv_prefix; return; } /* Set the default value for a port of a circuit model */ -void CircuitLibrary::set_port_default_value(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_default_value(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& default_value) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_default_values_[circuit_model_id][circuit_port_id] = default_value; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_default_values_[model_id][circuit_port_id] = default_value; return; } /* Set the is_mode_select for a port of a circuit model */ -void CircuitLibrary::set_port_is_mode_select(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_is_mode_select(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_mode_select) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_is_mode_select_[circuit_model_id][circuit_port_id] = is_mode_select; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_is_mode_select_[model_id][circuit_port_id] = is_mode_select; return; } /* Set the is_global for a port of a circuit model */ -void CircuitLibrary::set_port_is_global(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_is_global(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_global) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_is_global_[circuit_model_id][circuit_port_id] = is_global; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_is_global_[model_id][circuit_port_id] = is_global; return; } /* Set the is_reset for a port of a circuit model */ -void CircuitLibrary::set_port_is_reset(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_is_reset(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_reset) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_is_reset_[circuit_model_id][circuit_port_id] = is_reset; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_is_reset_[model_id][circuit_port_id] = is_reset; return; } /* Set the is_set for a port of a circuit model */ -void CircuitLibrary::set_port_is_set(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_is_set(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_set) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_is_set_[circuit_model_id][circuit_port_id] = is_set; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_is_set_[model_id][circuit_port_id] = is_set; return; } /* Set the is_config_enable for a port of a circuit model */ -void CircuitLibrary::set_port_is_config_enable(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_is_config_enable(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_config_enable) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_is_config_enable_[circuit_model_id][circuit_port_id] = is_config_enable; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_is_config_enable_[model_id][circuit_port_id] = is_config_enable; return; } /* Set the is_prog for a port of a circuit model */ -void CircuitLibrary::set_port_is_prog(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_is_prog(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_prog) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_is_prog_[circuit_model_id][circuit_port_id] = is_prog; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_is_prog_[model_id][circuit_port_id] = is_prog; return; } -/* Set the circuit_model_name for a port of a circuit model */ -void CircuitLibrary::set_port_circuit_model_name(const CircuitModelId& circuit_model_id, +/* Set the model_name for a port of a circuit model */ +void CircuitLibrary::set_port_model_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const std::string& circuit_model_name) { + const std::string& model_name) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_circuit_model_names_[circuit_model_id][circuit_port_id] = circuit_model_name; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_model_names_[model_id][circuit_port_id] = model_name; return; } -/* Set the circuit_model_id for a port of a circuit model */ -void CircuitLibrary::set_port_circuit_model_id(const CircuitModelId& circuit_model_id, +/* Set the model_id for a port of a circuit model */ +void CircuitLibrary::set_port_model_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const CircuitModelId& port_circuit_model_id) { + const CircuitModelId& port_model_id) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_circuit_model_ids_[circuit_model_id][circuit_port_id] = port_circuit_model_id; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_model_ids_[model_id][circuit_port_id] = port_model_id; return; } -/* Set the inv_circuit_model_name for a port of a circuit model */ -void CircuitLibrary::set_port_inv_circuit_model_name(const CircuitModelId& circuit_model_id, +/* Set the inv_model_name for a port of a circuit model */ +void CircuitLibrary::set_port_inv_model_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const std::string& inv_circuit_model_name) { + const std::string& inv_model_name) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_inv_circuit_model_names_[circuit_model_id][circuit_port_id] = inv_circuit_model_name; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_inv_model_names_[model_id][circuit_port_id] = inv_model_name; return; } -/* Set the inv_circuit_model_id for a port of a circuit model */ -void CircuitLibrary::set_port_inv_circuit_model_id(const CircuitModelId& circuit_model_id, +/* Set the inv_model_id for a port of a circuit model */ +void CircuitLibrary::set_port_inv_model_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const CircuitModelId& inv_circuit_model_id) { + const CircuitModelId& inv_model_id) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_inv_circuit_model_ids_[circuit_model_id][circuit_port_id] = inv_circuit_model_id; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_inv_model_ids_[model_id][circuit_port_id] = inv_model_id; return; } /* Set the tri-state map for a port of a circuit model */ -void CircuitLibrary::set_port_tri_state_map(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_tri_state_map(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& tri_state_map) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - port_tri_state_maps_[circuit_model_id][circuit_port_id] = tri_state_map; + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + port_tri_state_maps_[model_id][circuit_port_id] = tri_state_map; return; } /* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */ -void CircuitLibrary::set_port_lut_frac_level(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_lut_frac_level(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& lut_frac_level) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); /* Make sure this is a LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); - port_lut_frac_level_[circuit_model_id][circuit_port_id] = lut_frac_level; + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + port_lut_frac_level_[model_id][circuit_port_id] = lut_frac_level; return; } /* Set the LUT fracturable level for a port of a circuit model, only applicable to LUTs */ -void CircuitLibrary::set_port_lut_output_mask(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_lut_output_mask(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::vector& lut_output_masks) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); /* Make sure this is a LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); - port_lut_output_masks_[circuit_model_id][circuit_port_id] = lut_output_masks; + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + port_lut_output_masks_[model_id][circuit_port_id] = lut_output_masks; return; } /* Set the SRAM organization for a port of a circuit model, only applicable to SRAM ports */ -void CircuitLibrary::set_port_sram_orgz(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_port_sram_orgz(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const enum e_sram_orgz& sram_orgz) { /* validate the circuit_port_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); /* Make sure this is a SRAM port */ - VTR_ASSERT(SPICE_MODEL_PORT_SRAM == port_type(circuit_model_id, circuit_port_id)); - port_sram_orgz_[circuit_model_id][circuit_port_id] = sram_orgz; + VTR_ASSERT(SPICE_MODEL_PORT_SRAM == port_type(model_id, circuit_port_id)); + port_sram_orgz_[model_id][circuit_port_id] = sram_orgz; return; } @@ -1066,311 +1066,311 @@ void CircuitLibrary::set_port_sram_orgz(const CircuitModelId& circuit_model_id, * if yes, assign values * if no, resize and assign values */ -void CircuitLibrary::add_delay_info(const CircuitModelId& circuit_model_id, +void CircuitLibrary::add_delay_info(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Check the range of vector */ - if (size_t(delay_type) >= delay_types_[circuit_model_id].size()) { + if (size_t(delay_type) >= delay_types_[model_id].size()) { /* Resize */ - delay_types_[circuit_model_id].resize(size_t(delay_type) + 1); - delay_in_port_names_[circuit_model_id].resize(size_t(delay_type) + 1); - delay_out_port_names_[circuit_model_id].resize(size_t(delay_type) + 1); - delay_values_[circuit_model_id].resize(size_t(delay_type) + 1); + delay_types_[model_id].resize(size_t(delay_type) + 1); + delay_in_port_names_[model_id].resize(size_t(delay_type) + 1); + delay_out_port_names_[model_id].resize(size_t(delay_type) + 1); + delay_values_[model_id].resize(size_t(delay_type) + 1); } - delay_types_[circuit_model_id][size_t(delay_type)] = delay_type; + delay_types_[model_id][size_t(delay_type)] = delay_type; return; } -void CircuitLibrary::set_delay_in_port_names(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_delay_in_port_names(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type, const std::string& in_port_names) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Validate delay_type */ - VTR_ASSERT(valid_delay_type(circuit_model_id, delay_type)); - delay_in_port_names_[circuit_model_id][size_t(delay_type)] = in_port_names; + VTR_ASSERT(valid_delay_type(model_id, delay_type)); + delay_in_port_names_[model_id][size_t(delay_type)] = in_port_names; return; } -void CircuitLibrary::set_delay_out_port_names(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_delay_out_port_names(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type, const std::string& out_port_names) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Validate delay_type */ - VTR_ASSERT(valid_delay_type(circuit_model_id, delay_type)); - delay_out_port_names_[circuit_model_id][size_t(delay_type)] = out_port_names; + VTR_ASSERT(valid_delay_type(model_id, delay_type)); + delay_out_port_names_[model_id][size_t(delay_type)] = out_port_names; return; } -void CircuitLibrary::set_delay_values(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_delay_values(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type, const std::string& delay_values) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Validate delay_type */ - VTR_ASSERT(valid_delay_type(circuit_model_id, delay_type)); - delay_values_[circuit_model_id][size_t(delay_type)] = delay_values; + VTR_ASSERT(valid_delay_type(model_id, delay_type)); + delay_values_[model_id][size_t(delay_type)] = delay_values; return; } /* Buffer/Inverter-related parameters */ -void CircuitLibrary::set_buffer_type(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_buffer_type(const CircuitModelId& model_id, const enum e_spice_model_buffer_type& buffer_type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); - buffer_types_[circuit_model_id] = buffer_type; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); + buffer_types_[model_id] = buffer_type; return; } -void CircuitLibrary::set_buffer_size(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_buffer_size(const CircuitModelId& model_id, const float& buffer_size) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); - buffer_sizes_[circuit_model_id] = buffer_size; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); + buffer_sizes_[model_id] = buffer_size; return; } -void CircuitLibrary::set_buffer_num_levels(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_buffer_num_levels(const CircuitModelId& model_id, const size_t& num_levels) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); - buffer_num_levels_[circuit_model_id] = num_levels; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); + buffer_num_levels_[model_id] = num_levels; return; } -void CircuitLibrary::set_buffer_f_per_stage(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_buffer_f_per_stage(const CircuitModelId& model_id, const size_t& f_per_stage) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_INVBUF == circuit_model_type(circuit_model_id)); - buffer_f_per_stage_[circuit_model_id] = f_per_stage; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_INVBUF == model_type(model_id)); + buffer_f_per_stage_[model_id] = f_per_stage; return; } /* Pass-gate-related parameters */ -void CircuitLibrary::set_pass_gate_logic_type(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_pass_gate_logic_type(const CircuitModelId& model_id, const enum e_spice_model_pass_gate_logic_type& pass_gate_logic_type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); - pass_gate_logic_types_[circuit_model_id] = pass_gate_logic_type; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_PASSGATE == model_type(model_id)); + pass_gate_logic_types_[model_id] = pass_gate_logic_type; return; } -void CircuitLibrary::set_pass_gate_logic_nmos_size(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_pass_gate_logic_nmos_size(const CircuitModelId& model_id, const float& nmos_size) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); - pass_gate_logic_sizes_[circuit_model_id].set_x(nmos_size); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_PASSGATE == model_type(model_id)); + pass_gate_logic_sizes_[model_id].set_x(nmos_size); return; } -void CircuitLibrary::set_pass_gate_logic_pmos_size(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_pass_gate_logic_pmos_size(const CircuitModelId& model_id, const float& pmos_size) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be BUFFER or INVERTER */ - VTR_ASSERT(SPICE_MODEL_PASSGATE == circuit_model_type(circuit_model_id)); - pass_gate_logic_sizes_[circuit_model_id].set_y(pmos_size); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be BUFFER or INVERTER */ + VTR_ASSERT(SPICE_MODEL_PASSGATE == model_type(model_id)); + pass_gate_logic_sizes_[model_id].set_y(pmos_size); return; } /* Multiplexer-related parameters */ -void CircuitLibrary::set_mux_structure(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_mux_structure(const CircuitModelId& model_id, const enum e_spice_model_structure& mux_structure) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); - mux_structure_[circuit_model_id] = mux_structure; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); + mux_structure_[model_id] = mux_structure; return; } -void CircuitLibrary::set_mux_num_levels(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_mux_num_levels(const CircuitModelId& model_id, const size_t& num_levels) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); - mux_num_levels_[circuit_model_id] = num_levels; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); + mux_num_levels_[model_id] = num_levels; return; } -void CircuitLibrary::set_mux_const_input_value(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_mux_const_input_value(const CircuitModelId& model_id, const size_t& const_input_value) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); /* validate the const input values */ VTR_ASSERT( valid_mux_const_input_value(const_input_value) ); - mux_const_input_values_[circuit_model_id] = const_input_value; + mux_const_input_values_[model_id] = const_input_value; return; } -void CircuitLibrary::set_mux_use_local_encoder(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_mux_use_local_encoder(const CircuitModelId& model_id, const bool& use_local_encoder) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); - mux_use_local_encoder_[circuit_model_id] = use_local_encoder; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); + mux_use_local_encoder_[model_id] = use_local_encoder; return; } -void CircuitLibrary::set_mux_use_advanced_rram_design(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_mux_use_advanced_rram_design(const CircuitModelId& model_id, const bool& use_advanced_rram_design) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be MUX or LUT */ - VTR_ASSERT( (SPICE_MODEL_MUX == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)) ); - mux_use_advanced_rram_design_[circuit_model_id] = use_advanced_rram_design; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be MUX or LUT */ + VTR_ASSERT( (SPICE_MODEL_MUX == model_type(model_id)) + || (SPICE_MODEL_LUT == model_type(model_id)) ); + mux_use_advanced_rram_design_[model_id] = use_advanced_rram_design; return; } /* LUT-related parameters */ -void CircuitLibrary::set_lut_is_fracturable(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_lut_is_fracturable(const CircuitModelId& model_id, const bool& is_fracturable) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be LUT */ - VTR_ASSERT(SPICE_MODEL_LUT == circuit_model_type(circuit_model_id)); - lut_is_fracturable_[circuit_model_id] = is_fracturable; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be LUT */ + VTR_ASSERT(SPICE_MODEL_LUT == model_type(model_id)); + lut_is_fracturable_[model_id] = is_fracturable; return; } /* Gate-related parameters */ -void CircuitLibrary::set_gate_type(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_gate_type(const CircuitModelId& model_id, const enum e_spice_model_gate_type& gate_type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be GATE */ - VTR_ASSERT(SPICE_MODEL_GATE == circuit_model_type(circuit_model_id)); - gate_types_[circuit_model_id] = gate_type; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be GATE */ + VTR_ASSERT(SPICE_MODEL_GATE == model_type(model_id)); + gate_types_[model_id] = gate_type; return; } /* RRAM-related design technology information */ -void CircuitLibrary::set_rram_rlrs(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_rram_rlrs(const CircuitModelId& model_id, const float& rlrs) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); - rram_res_[circuit_model_id].set_x(rlrs); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + rram_res_[model_id].set_x(rlrs); return; } -void CircuitLibrary::set_rram_rhrs(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_rram_rhrs(const CircuitModelId& model_id, const float& rhrs) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); - rram_res_[circuit_model_id].set_y(rhrs); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + rram_res_[model_id].set_y(rhrs); return; } -void CircuitLibrary::set_rram_wprog_set_nmos(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_rram_wprog_set_nmos(const CircuitModelId& model_id, const float& wprog_set_nmos) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); - wprog_set_[circuit_model_id].set_x(wprog_set_nmos); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + wprog_set_[model_id].set_x(wprog_set_nmos); return; } -void CircuitLibrary::set_rram_wprog_set_pmos(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_rram_wprog_set_pmos(const CircuitModelId& model_id, const float& wprog_set_pmos) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); - wprog_set_[circuit_model_id].set_y(wprog_set_pmos); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + wprog_set_[model_id].set_y(wprog_set_pmos); return; } -void CircuitLibrary::set_rram_wprog_reset_nmos(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_rram_wprog_reset_nmos(const CircuitModelId& model_id, const float& wprog_reset_nmos) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); - wprog_reset_[circuit_model_id].set_x(wprog_reset_nmos); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + wprog_reset_[model_id].set_x(wprog_reset_nmos); return; } -void CircuitLibrary::set_rram_wprog_reset_pmos(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_rram_wprog_reset_pmos(const CircuitModelId& model_id, const float& wprog_reset_pmos) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the design_tech of this circuit_model should be RRAM */ - VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(circuit_model_id)); - wprog_reset_[circuit_model_id].set_y(wprog_reset_pmos); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the design_tech of this model should be RRAM */ + VTR_ASSERT(SPICE_MODEL_DESIGN_RRAM == design_tech_type(model_id)); + wprog_reset_[model_id].set_y(wprog_reset_pmos); return; } /* Wire parameters */ -void CircuitLibrary::set_wire_type(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_wire_type(const CircuitModelId& model_id, const enum e_wire_model_type& wire_type) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ - VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); - wire_types_[circuit_model_id] = wire_type; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be WIRE or CHAN_WIRE */ + VTR_ASSERT( (SPICE_MODEL_WIRE == model_type(model_id)) + || (SPICE_MODEL_CHAN_WIRE == model_type(model_id)) ); + wire_types_[model_id] = wire_type; return; } -void CircuitLibrary::set_wire_r(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_wire_r(const CircuitModelId& model_id, const float& r_val) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ - VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); - wire_rc_[circuit_model_id].set_x(r_val); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be WIRE or CHAN_WIRE */ + VTR_ASSERT( (SPICE_MODEL_WIRE == model_type(model_id)) + || (SPICE_MODEL_CHAN_WIRE == model_type(model_id)) ); + wire_rc_[model_id].set_x(r_val); return; } -void CircuitLibrary::set_wire_c(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_wire_c(const CircuitModelId& model_id, const float& c_val) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ - VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); - wire_rc_[circuit_model_id].set_y(c_val); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be WIRE or CHAN_WIRE */ + VTR_ASSERT( (SPICE_MODEL_WIRE == model_type(model_id)) + || (SPICE_MODEL_CHAN_WIRE == model_type(model_id)) ); + wire_rc_[model_id].set_y(c_val); return; } -void CircuitLibrary::set_wire_num_levels(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_wire_num_levels(const CircuitModelId& model_id, const size_t& num_level) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - /* validate that the type of this circuit_model should be WIRE or CHAN_WIRE */ - VTR_ASSERT( (SPICE_MODEL_WIRE == circuit_model_type(circuit_model_id)) - || (SPICE_MODEL_CHAN_WIRE == circuit_model_type(circuit_model_id)) ); - wire_num_levels_[circuit_model_id] = num_level; + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + /* validate that the type of this model should be WIRE or CHAN_WIRE */ + VTR_ASSERT( (SPICE_MODEL_WIRE == model_type(model_id)) + || (SPICE_MODEL_CHAN_WIRE == model_type(model_id)) ); + wire_num_levels_[model_id] = num_level; return; } @@ -1382,130 +1382,130 @@ void CircuitLibrary::set_wire_num_levels(const CircuitModelId& circuit_model_id, * If yes, just assign values * If no, resize the vector and then assign values */ -void CircuitLibrary::set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, - const bool& existence, const std::string& circuit_model_name) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::set_model_buffer(const CircuitModelId& model_id, const enum e_buffer_type buffer_type, + const bool& existence, const std::string& model_name) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Check the range of vector */ - if (size_t(buffer_type) >= buffer_existence_[circuit_model_id].size()) { + if (size_t(buffer_type) >= buffer_existence_[model_id].size()) { /* Resize and assign values */ - buffer_existence_[circuit_model_id].resize(size_t(buffer_type) + 1); - buffer_circuit_model_names_[circuit_model_id].resize(size_t(buffer_type) + 1); - buffer_circuit_model_ids_[circuit_model_id].resize(size_t(buffer_type) + 1); - buffer_location_maps_[circuit_model_id].resize(size_t(buffer_type) + 1); + buffer_existence_[model_id].resize(size_t(buffer_type) + 1); + buffer_model_names_[model_id].resize(size_t(buffer_type) + 1); + buffer_model_ids_[model_id].resize(size_t(buffer_type) + 1); + buffer_location_maps_[model_id].resize(size_t(buffer_type) + 1); } /* Now we are in the range, assign values */ - buffer_existence_[circuit_model_id][size_t(buffer_type)] = existence; - buffer_circuit_model_names_[circuit_model_id][size_t(buffer_type)] = circuit_model_name; - buffer_circuit_model_ids_[circuit_model_id][size_t(buffer_type)] = CIRCUIT_MODEL_OPEN_ID; /* Set an OPEN id here, which will be linked later */ + buffer_existence_[model_id][size_t(buffer_type)] = existence; + buffer_model_names_[model_id][size_t(buffer_type)] = model_name; + buffer_model_ids_[model_id][size_t(buffer_type)] = CircuitModelId::INVALID(); /* Set an OPEN id here, which will be linked later */ return; } -/* Link the circuit_model_id for each port of a circuit model. - * We search the inv_circuit_model_name in the CircuitLibrary and - * configure the port inv_circuit_model_id +/* Link the model_id for each port of a circuit model. + * We search the inv_model_name in the CircuitLibrary and + * configure the port inv_model_id */ -void CircuitLibrary::link_port_circuit_model(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::link_port_model(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Walk through each ports, get the port id and find the circuit model id by name */ - for (auto& port_id : ports(circuit_model_id)) { + for (auto& port_id : ports(model_id)) { /* Bypass empty name */ - if (true == port_circuit_model_names_[circuit_model_id][port_id].empty()) { + if (true == port_model_names_[model_id][port_id].empty()) { continue; } - port_circuit_model_ids_[circuit_model_id][port_id] = circuit_model(port_circuit_model_names_[circuit_model_id][port_id]); + port_model_ids_[model_id][port_id] = model(port_model_names_[model_id][port_id]); } return; } -/* Link the inv_circuit_model_id for each port of a circuit model. - * We search the inv_circuit_model_name in the CircuitLibrary and - * configure the port inv_circuit_model_id +/* Link the inv_model_id for each port of a circuit model. + * We search the inv_model_name in the CircuitLibrary and + * configure the port inv_model_id */ -void CircuitLibrary::link_port_inv_circuit_model(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::link_port_inv_model(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Walk through each ports, get the port id and find the circuit model id by name */ - for (auto& port_id : ports(circuit_model_id)) { + for (auto& port_id : ports(model_id)) { /* Bypass empty name */ - if (true == port_inv_circuit_model_names_[circuit_model_id][port_id].empty()) { + if (true == port_inv_model_names_[model_id][port_id].empty()) { continue; } - port_inv_circuit_model_ids_[circuit_model_id][port_id] = circuit_model(port_inv_circuit_model_names_[circuit_model_id][port_id]); + port_inv_model_ids_[model_id][port_id] = model(port_inv_model_names_[model_id][port_id]); } return; } /* Link all the circuit model ids for each port of a circuit model */ -void CircuitLibrary::link_port_circuit_models(const CircuitModelId& circuit_model_id) { - link_port_circuit_model(circuit_model_id); - link_port_inv_circuit_model(circuit_model_id); +void CircuitLibrary::link_port_models(const CircuitModelId& model_id) { + link_port_model(model_id); + link_port_inv_model(model_id); return; } -/* Link the buffer_circuit_model - * We search the buffer_circuit_model_name in the CircuitLibrary and - * configure the buffer_circuit_model_id +/* Link the buffer_model + * We search the buffer_model_name in the CircuitLibrary and + * configure the buffer_model_id */ -void CircuitLibrary::link_buffer_circuit_model(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::link_buffer_model(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Get the circuit model id by name, skip those with empty names*/ - for (size_t buffer_id = 0; buffer_id < buffer_circuit_model_names_[circuit_model_id].size(); ++buffer_id) { - if (true == buffer_circuit_model_names_[circuit_model_id][buffer_id].empty()) { + for (size_t buffer_id = 0; buffer_id < buffer_model_names_[model_id].size(); ++buffer_id) { + if (true == buffer_model_names_[model_id][buffer_id].empty()) { return; } - buffer_circuit_model_ids_[circuit_model_id][buffer_id] = circuit_model(buffer_circuit_model_names_[circuit_model_id][buffer_id]); + buffer_model_ids_[model_id][buffer_id] = model(buffer_model_names_[model_id][buffer_id]); } return; } -/* Link the buffer_circuit_model - * We search the buffer_circuit_model_name in the CircuitLibrary and - * configure the buffer_circuit_model_id +/* Link the buffer_model + * We search the buffer_model_name in the CircuitLibrary and + * configure the buffer_model_id */ -void CircuitLibrary::link_pass_gate_logic_circuit_model(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::link_pass_gate_logic_model(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Get the circuit model id by name, skip those with empty names*/ - if (true == pass_gate_logic_circuit_model_names_[circuit_model_id].empty()) { + if (true == pass_gate_logic_model_names_[model_id].empty()) { return; } - pass_gate_logic_circuit_model_ids_[circuit_model_id] = circuit_model(pass_gate_logic_circuit_model_names_[circuit_model_id]); + pass_gate_logic_model_ids_[model_id] = model(pass_gate_logic_model_names_[model_id]); return; } -/* Build the links for attributes of each circuit_model by searching the circuit_model_names */ -void CircuitLibrary::build_circuit_model_links() { +/* Build the links for attributes of each model by searching the model_names */ +void CircuitLibrary::build_model_links() { /* Walk through each circuit model, build links one by one */ - for (auto& circuit_model_id : circuit_models()) { - /* Build links for buffers, pass-gates circuit_model */ - link_buffer_circuit_model(circuit_model_id); - link_pass_gate_logic_circuit_model(circuit_model_id); + for (auto& model_id : models()) { + /* Build links for buffers, pass-gates model */ + link_buffer_model(model_id); + link_pass_gate_logic_model(model_id); /* Build links for ports */ - link_port_circuit_models(circuit_model_id); + link_port_models(model_id); } return; } /* Build the timing graph for a circuit models*/ -void CircuitLibrary::build_circuit_model_timing_graph(const CircuitModelId& circuit_model_id) { +void CircuitLibrary::build_model_timing_graph(const CircuitModelId& model_id) { /* Now we start allocating a timing graph * Add outgoing edges for each input pin of the circuit model */ - for (auto& from_port_id : input_ports(circuit_model_id)) { + for (auto& from_port_id : input_ports(model_id)) { /* Add edges for each input pin */ - for (auto& from_pin_id : pins(circuit_model_id, from_port_id)) { + for (auto& from_pin_id : pins(model_id, from_port_id)) { /* We should walk through output pins here */ - for (auto& to_port_id : output_ports(circuit_model_id)) { - for (auto& to_pin_id : pins(circuit_model_id, to_port_id)) { + for (auto& to_port_id : output_ports(model_id)) { + for (auto& to_pin_id : pins(model_id, to_port_id)) { /* Skip self-loops */ if (from_port_id == to_port_id) { continue; } /* Add an edge to bridge the from_pin_id and to_pin_id */ - add_edge(circuit_model_id, from_port_id, from_pin_id, to_port_id, to_pin_id); + add_edge(model_id, from_port_id, from_pin_id, to_port_id, to_pin_id); } } } @@ -1516,12 +1516,12 @@ void CircuitLibrary::build_circuit_model_timing_graph(const CircuitModelId& circ /* Build the timing graph for a circuit models*/ void CircuitLibrary::build_timing_graphs() { /* Walk through each circuit model, build timing graph one by one */ - for (auto& circuit_model_id : circuit_models()) { + for (auto& model_id : models()) { /* Free the timing graph if it already exists, we will rebuild one */ - invalidate_circuit_model_timing_graph(circuit_model_id); - build_circuit_model_timing_graph(circuit_model_id); + invalidate_model_timing_graph(model_id); + build_model_timing_graph(model_id); /* Annotate timing information */ - set_timing_graph_delays(circuit_model_id); + set_timing_graph_delays(model_id); } return; } @@ -1530,66 +1530,66 @@ void CircuitLibrary::build_timing_graphs() { * Internal mutators: build timing graphs ***********************************************************************/ /* Add an edge between two pins of two ports, and assign an default timing value */ -void CircuitLibrary::add_edge(const CircuitModelId& circuit_model_id, +void CircuitLibrary::add_edge(const CircuitModelId& model_id, const CircuitPortId& from_port, const size_t& from_pin, const CircuitPortId& to_port, const size_t& to_pin) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Create an edge in the edge id list */ - CircuitEdgeId edge_id = CircuitEdgeId(edge_ids_[circuit_model_id].size()); + CircuitEdgeId edge_id = CircuitEdgeId(edge_ids_[model_id].size()); /* Expand the edge list */ - edge_ids_[circuit_model_id].push_back(edge_id); + edge_ids_[model_id].push_back(edge_id); /* Initialize other attributes */ /* Update the list of incoming edges for to_port */ /* Resize upon need */ - if (to_pin >= port_in_edge_ids_[circuit_model_id][to_port].size()) { - port_in_edge_ids_[circuit_model_id][to_port].resize(to_pin + 1); + if (to_pin >= port_in_edge_ids_[model_id][to_port].size()) { + port_in_edge_ids_[model_id][to_port].resize(to_pin + 1); } - port_in_edge_ids_[circuit_model_id][to_port][to_pin] = edge_id; + port_in_edge_ids_[model_id][to_port][to_pin] = edge_id; /* Update the list of outgoing edges for from_port */ /* Resize upon need */ - if (from_pin >= port_out_edge_ids_[circuit_model_id][from_port].size()) { - port_out_edge_ids_[circuit_model_id][from_port].resize(from_pin + 1); + if (from_pin >= port_out_edge_ids_[model_id][from_port].size()) { + port_out_edge_ids_[model_id][from_port].resize(from_pin + 1); } - port_out_edge_ids_[circuit_model_id][from_port][from_pin] = edge_id; + port_out_edge_ids_[model_id][from_port][from_pin] = edge_id; /* Update source ports and pins of the edge */ - edge_src_port_ids_[circuit_model_id].push_back(from_port); - edge_src_pin_ids_[circuit_model_id].push_back(from_pin); + edge_src_port_ids_[model_id].push_back(from_port); + edge_src_pin_ids_[model_id].push_back(from_pin); /* Update sink ports and pins of the edge */ - edge_sink_port_ids_[circuit_model_id].push_back(to_port); - edge_sink_pin_ids_[circuit_model_id].push_back(to_pin); + edge_sink_port_ids_[model_id].push_back(to_port); + edge_sink_pin_ids_[model_id].push_back(to_pin); /* Give a default value for timing values */ std::vector timing_info(NUM_CIRCUIT_MODEL_DELAY_TYPES, 0); - edge_timing_info_[circuit_model_id].push_back(timing_info); + edge_timing_info_[model_id].push_back(timing_info); return; } -void CircuitLibrary::set_edge_delay(const CircuitModelId& circuit_model_id, +void CircuitLibrary::set_edge_delay(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id, const enum spice_model_delay_type& delay_type, const float& delay_value) { /* validate the circuit_edge_id */ - VTR_ASSERT(valid_circuit_edge_id(circuit_model_id, circuit_edge_id)); - VTR_ASSERT(valid_delay_type(circuit_model_id, delay_type)); + VTR_ASSERT(valid_circuit_edge_id(model_id, circuit_edge_id)); + VTR_ASSERT(valid_delay_type(model_id, delay_type)); - edge_timing_info_[circuit_model_id][circuit_edge_id][size_t(delay_type)] = delay_value; + edge_timing_info_[model_id][circuit_edge_id][size_t(delay_type)] = delay_value; return; } /* Annotate delay values on a timing graph */ -void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); +void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); /* Go one delay_info by another */ - for (const auto& delay_type : delay_types_[circuit_model_id]) { + for (const auto& delay_type : delay_types_[model_id]) { /* Parse the input port names and output names. * We will store the parsing results in vectors: * 1. vector for port ids for each port name @@ -1597,65 +1597,65 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model */ /* Parse the string for inputs */ - MultiPortParser input_port_parser(delay_in_port_names_[circuit_model_id][size_t(delay_type)]); + MultiPortParser input_port_parser(delay_in_port_names_[model_id][size_t(delay_type)]); std::vector input_ports = input_port_parser.ports(); std::vector input_port_ids; std::vector input_pin_ids; /* Check each element */ for (auto& port_info : input_ports) { /* Try to find a port by the given name */ - CircuitPortId port_id = port(circuit_model_id, port_info.get_name()); + CircuitPortId port_id = port(model_id, port_info.get_name()); /* We must have a valid port and Port width must be 1! */ - VTR_ASSERT(CIRCUIT_PORT_OPEN_ID != port_id); + VTR_ASSERT(CircuitPortId::INVALID() != port_id); if (0 == port_info.get_width()) { /* we need to configure the port width if it is zero. * This means that parser find some compact port defintion such as */ - size_t port_width = port_size(circuit_model_id, port_id); + size_t port_width = port_size(model_id, port_id); port_info.set_width(port_width); } else { VTR_ASSERT(1 == port_info.get_width()); } /* The pin id should be valid! */ - VTR_ASSERT(true == valid_circuit_pin_id(circuit_model_id, port_id, port_info.get_lsb())); + VTR_ASSERT(true == valid_circuit_pin_id(model_id, port_id, port_info.get_lsb())); /* This must be an input port! */ - VTR_ASSERT(true == is_input_port(circuit_model_id, port_id)); + VTR_ASSERT(true == is_input_port(model_id, port_id)); /* Push to */ input_port_ids.push_back(port_id); input_pin_ids.push_back(port_info.get_lsb()); } /* Parse the string for outputs */ - MultiPortParser output_port_parser(delay_out_port_names_[circuit_model_id][size_t(delay_type)]); + MultiPortParser output_port_parser(delay_out_port_names_[model_id][size_t(delay_type)]); std::vector output_ports = output_port_parser.ports(); std::vector output_port_ids; std::vector output_pin_ids; /* Check each element */ for (auto& port_info : output_ports) { /* Try to find a port by the given name */ - CircuitPortId port_id = port(circuit_model_id, port_info.get_name()); + CircuitPortId port_id = port(model_id, port_info.get_name()); /* We must have a valid port and Port width must be 1! */ - VTR_ASSERT(CIRCUIT_PORT_OPEN_ID != port_id); + VTR_ASSERT(CircuitPortId::INVALID() != port_id); if (0 == port_info.get_width()) { /* we need to configure the port width if it is zero. * This means that parser find some compact port defintion such as */ - size_t port_width = port_size(circuit_model_id, port_id); + size_t port_width = port_size(model_id, port_id); port_info.set_width(port_width); } else { VTR_ASSERT(1 == port_info.get_width()); } /* The pin id should be valid! */ - VTR_ASSERT(true == valid_circuit_pin_id(circuit_model_id, port_id, port_info.get_lsb())); + VTR_ASSERT(true == valid_circuit_pin_id(model_id, port_id, port_info.get_lsb())); /* This must be an output port! */ - VTR_ASSERT(true == is_output_port(circuit_model_id, port_id)); + VTR_ASSERT(true == is_output_port(model_id, port_id)); /* Push to */ output_port_ids.push_back(port_id); output_pin_ids.push_back(port_info.get_lsb()); } /* Parse the delay matrix */ - PortDelayParser port_delay_parser(delay_values_[circuit_model_id][size_t(delay_type)]); + PortDelayParser port_delay_parser(delay_values_[model_id][size_t(delay_type)]); /* Make sure the delay matrix size matches */ VTR_ASSERT(port_delay_parser.height() == output_port_ids.size()); @@ -1667,12 +1667,12 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model for (size_t i = 0; i < port_delay_parser.height(); ++i) { for (size_t j = 0; j < port_delay_parser.width(); ++j) { float delay_value = port_delay_parser.delay(i, j); - CircuitEdgeId edge_id = edge(circuit_model_id, + CircuitEdgeId edge_id = edge(model_id, input_port_ids[j], input_pin_ids[j], output_port_ids[i], output_pin_ids[i]); /* make sure we have an valid edge_id */ - VTR_ASSERT(true == valid_circuit_edge_id(circuit_model_id, edge_id)); - set_edge_delay(circuit_model_id, edge_id, + VTR_ASSERT(true == valid_circuit_edge_id(model_id, edge_id)); + set_edge_delay(model_id, edge_id, delay_type, delay_value); } } @@ -1684,28 +1684,28 @@ void CircuitLibrary::set_timing_graph_delays(const CircuitModelId& circuit_model * Internal mutators: build fast look-ups ***********************************************************************/ /* Build fast look-up for circuit models */ -void CircuitLibrary::build_circuit_model_lookup() { +void CircuitLibrary::build_model_lookup() { /* invalidate fast look-up */ - invalidate_circuit_model_lookup(); + invalidate_model_lookup(); /* Classify circuit models by type */ - circuit_model_lookup_.resize(NUM_CIRCUIT_MODEL_TYPES); - /* Walk through circuit_models and categorize */ - for (auto& id : circuit_model_ids_) { - circuit_model_lookup_[circuit_model_types_[id]].push_back(id); + model_lookup_.resize(NUM_CIRCUIT_MODEL_TYPES); + /* Walk through models and categorize */ + for (auto& id : model_ids_) { + model_lookup_[model_types_[id]].push_back(id); } - /* Make the default circuit_model to be the first element for each type */ - for (auto& type : circuit_model_lookup_) { + /* Make the default model to be the first element for each type */ + for (auto& type : model_lookup_) { /* Skip zero-length parts of look-up */ if (true == type.empty()) { continue; } /* if the first element is already a default model, we skip this */ - if (true == circuit_model_is_default_[type[0]]) { + if (true == model_is_default_[type[0]]) { continue; } /* Check the array, and try to find a default model */ for (size_t id = 0; id < type.size(); ++id) { - if (false == circuit_model_is_default_[type[id]]) { + if (false == model_is_default_[type[id]]) { continue; } /* Once we find a default model, swap with the first element and finish the loop */ @@ -1717,14 +1717,14 @@ void CircuitLibrary::build_circuit_model_lookup() { } /* Build fast look-up for circuit model ports */ -void CircuitLibrary::build_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) { +void CircuitLibrary::build_model_port_lookup(const CircuitModelId& model_id) { /* invalidate fast look-up */ - invalidate_circuit_model_port_lookup(circuit_model_id); + invalidate_model_port_lookup(model_id); /* Classify circuit models by type */ - circuit_model_port_lookup_[size_t(circuit_model_id)].resize(NUM_CIRCUIT_MODEL_PORT_TYPES); - /* Walk through circuit_models and categorize */ - for (auto& port_id : port_ids_[circuit_model_id]) { - circuit_model_port_lookup_[size_t(circuit_model_id)][port_type(circuit_model_id, port_id)].push_back(port_id); + model_port_lookup_[size_t(model_id)].resize(NUM_CIRCUIT_MODEL_PORT_TYPES); + /* Walk through models and categorize */ + for (auto& port_id : port_ids_[model_id]) { + model_port_lookup_[size_t(model_id)][port_type(model_id, port_id)].push_back(port_id); } return; } @@ -1733,32 +1733,32 @@ void CircuitLibrary::build_circuit_model_port_lookup(const CircuitModelId& circu * Internal invalidators/validators ***********************************************************************/ /* Validators */ -bool CircuitLibrary::valid_circuit_model_id(const CircuitModelId& circuit_model_id) const { - return ( size_t(circuit_model_id) < circuit_model_ids_.size() ) && ( circuit_model_id == circuit_model_ids_[circuit_model_id] ); +bool CircuitLibrary::valid_model_id(const CircuitModelId& model_id) const { + return ( size_t(model_id) < model_ids_.size() ) && ( model_id == model_ids_[model_id] ); } -bool CircuitLibrary::valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return ( size_t(circuit_port_id) < port_ids_[circuit_model_id].size() ) && ( circuit_port_id == port_ids_[circuit_model_id][circuit_port_id] ); +bool CircuitLibrary::valid_circuit_port_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return ( size_t(circuit_port_id) < port_ids_[model_id].size() ) && ( circuit_port_id == port_ids_[model_id][circuit_port_id] ); } -bool CircuitLibrary::valid_circuit_pin_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_port_id(circuit_model_id, circuit_port_id)); - return ( size_t(pin_id) < port_size(circuit_model_id, circuit_port_id) ); +bool CircuitLibrary::valid_circuit_pin_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_circuit_port_id(model_id, circuit_port_id)); + return ( size_t(pin_id) < port_size(model_id, circuit_port_id) ); } -bool CircuitLibrary::valid_delay_type(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return ( size_t(delay_type) < delay_types_[circuit_model_id].size() ) && ( delay_type == delay_types_[circuit_model_id][size_t(delay_type)] ); +bool CircuitLibrary::valid_delay_type(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return ( size_t(delay_type) < delay_types_[model_id].size() ) && ( delay_type == delay_types_[model_id][size_t(delay_type)] ); } -bool CircuitLibrary::valid_circuit_edge_id(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - return ( size_t(circuit_edge_id) < edge_ids_[circuit_model_id].size() ) && ( circuit_edge_id == edge_ids_[circuit_model_id][circuit_edge_id] ); +bool CircuitLibrary::valid_circuit_edge_id(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + return ( size_t(circuit_edge_id) < edge_ids_[model_id].size() ) && ( circuit_edge_id == edge_ids_[model_id][circuit_edge_id] ); } /* Validate the value of constant input @@ -1774,38 +1774,38 @@ bool CircuitLibrary::valid_mux_const_input_value(const size_t& const_input_value } /* Invalidators */ -/* Empty fast lookup for circuit_models*/ -void CircuitLibrary::invalidate_circuit_model_lookup() const { - circuit_model_lookup_.clear(); +/* Empty fast lookup for models*/ +void CircuitLibrary::invalidate_model_lookup() const { + model_lookup_.clear(); return; } -/* Empty fast lookup for circuit ports for a circuit_model */ -void CircuitLibrary::invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - circuit_model_port_lookup_[size_t(circuit_model_id)].clear(); +/* Empty fast lookup for circuit ports for a model */ +void CircuitLibrary::invalidate_model_port_lookup(const CircuitModelId& model_id) const { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + model_port_lookup_[size_t(model_id)].clear(); return; } /* Clear all the data structure related to the timing graph */ -void CircuitLibrary::invalidate_circuit_model_timing_graph(const CircuitModelId& circuit_model_id) { - /* validate the circuit_model_id */ - VTR_ASSERT(valid_circuit_model_id(circuit_model_id)); - edge_ids_[circuit_model_id].clear(); +void CircuitLibrary::invalidate_model_timing_graph(const CircuitModelId& model_id) { + /* validate the model_id */ + VTR_ASSERT(valid_model_id(model_id)); + edge_ids_[model_id].clear(); - for (const auto& port_id : ports(circuit_model_id)) { - port_in_edge_ids_[circuit_model_id][port_id].clear(); - port_out_edge_ids_[circuit_model_id][port_id].clear(); + for (const auto& port_id : ports(model_id)) { + port_in_edge_ids_[model_id][port_id].clear(); + port_out_edge_ids_[model_id][port_id].clear(); } - edge_src_port_ids_[circuit_model_id].clear(); - edge_src_pin_ids_[circuit_model_id].clear(); + edge_src_port_ids_[model_id].clear(); + edge_src_pin_ids_[model_id].clear(); - edge_sink_port_ids_[circuit_model_id].clear(); - edge_sink_pin_ids_[circuit_model_id].clear(); + edge_sink_port_ids_[model_id].clear(); + edge_sink_pin_ids_[model_id].clear(); - edge_timing_info_[circuit_model_id].clear(); + edge_timing_info_[model_id].clear(); return; } diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library.h b/vpr7_x2p/libarchfpga/SRC/circuit_library.h index 211475098..a74429347 100644 --- a/vpr7_x2p/libarchfpga/SRC/circuit_library.h +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library.h @@ -49,7 +49,6 @@ /* Standard header files required go first */ #include -#include "vtr_strong_id.h" #include "vtr_geometry.h" #include "vtr_vector.h" @@ -57,22 +56,7 @@ #include "circuit_types.h" -/************************************************************************ - * Create strong id for Circuit Models/Ports to avoid illegal type casting - ***********************************************************************/ -struct circuit_model_id_tag; -struct circuit_port_id_tag; -struct circuit_edge_id_tag; - -typedef vtr::StrongId CircuitModelId; -typedef vtr::StrongId CircuitPortId; -typedef vtr::StrongId CircuitEdgeId; - - -/* Alias for open ids */ -#define CIRCUIT_MODEL_OPEN_ID CircuitModelId(-1) -#define CIRCUIT_PORT_OPEN_ID CircuitPortId(-1) -#define CIRCUIT_EDGE_OPEN_ID CircuitEdgeId(-1) +#include "circuit_library_fwd.h" /************************************************************************ * The class CircuitLibrary is a critical data structure for OpenFPGA @@ -81,20 +65,20 @@ typedef vtr::StrongId CircuitEdgeId; * It includes the following data: * * ------ Fundamental Information ----- - * 1. circuit_model_ids_ : unique identifier to find a circuit model + * 1. model_ids_ : unique identifier to find a circuit model * Use a strong id for search, to avoid illegal type casting - * 2. circuit_model_types_: types of the circuit model, see details in the definition of enum e_spice_model_type - * 3. circuit_model_names_: unique names for each circuit models. + * 2. model_types_: types of the circuit model, see details in the definition of enum e_spice_model_type + * 3. model_names_: unique names for each circuit models. * It should be the same as user-defined Verilog modules, if it is not auto-generated - * 4. circuit_model_prefix_: the prefix of a circuit model when it is instanciated + * 4. model_prefix_: the prefix of a circuit model when it is instanciated * 5. verilog_netlist_: specified path and file name of Verilog netlist if a circuit model is not auto-generated * 6. spice_netlist_: specified path and file name of SPICE netlist if a circuit model is not auto-generated * 7. is_default_: indicate if the circuit model is the default one among all those in the same type * * ------ Fast look-ups----- - * 1. circuit_model_lookup_: A multi-dimension vector to provide fast look-up on circuit models for users + * 1. model_lookup_: A multi-dimension vector to provide fast look-up on circuit models for users * It classifies CircuitModelIds by their type and set the default model in the first element for each type. - * 2. circuit_model_port_lookup_: A multi-dimension vector to provide fast look-up on ports of circuit models for users + * 2. model_port_lookup_: A multi-dimension vector to provide fast look-up on ports of circuit models for users * It classifies Ports by their types * * ------ Verilog generation options ----- @@ -109,12 +93,12 @@ typedef vtr::StrongId CircuitEdgeId; * Use vectors to simplify the defition of buffer existence: * index (low=0 to high) represents INPUT, OUTPUT, LUT_INPUT_BUF, LUT_INPUT_INV, LUT_INTER_BUFFER * 1. buffer_existence_: specify if this circuit model has an buffer - * 2. buffer_circuit_model_name_: specify the name of circuit model for the buffer - * 3. buffer_circuit_model_id_: specify the id of circuit model for the buffer + * 2. buffer_model_name_: specify the name of circuit model for the buffer + * 3. buffer_model_id_: specify the id of circuit model for the buffer * * ------ Pass-gate-related parameters ------ - * 1. pass_gate_logic_circuit_model_name_: specify the name of circuit model for the pass gate logic - * 2. pass_gate_logic_circuit_model_id_: specify the id of circuit model for the pass gate logic + * 1. pass_gate_logic_model_name_: specify the name of circuit model for the pass gate logic + * 2. pass_gate_logic_model_id_: specify the id of circuit model for the pass gate logic * * ------ Port information ------ * 1. port_ids_: unique id of ports belonging to a circuit model @@ -129,10 +113,10 @@ typedef vtr::StrongId CircuitEdgeId; * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches - * 13. port_circuit_model_name: the name of circuit model linked to the port - * 14. port_circuit_model_ids_: the Id of circuit model linked to the port - * 15. port_inv_circuit_model_names_: the name of inverter circuit model linked to the port - * 16. port_inv_circuit_model_ids_: the Id of inverter circuit model linked to the port + * 13. port_model_name: the name of circuit model linked to the port + * 14. port_model_ids_: the Id of circuit model linked to the port + * 15. port_inv_model_names_: the name of inverter circuit model linked to the port + * 16. port_inv_model_ids_: the Id of inverter circuit model linked to the port * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port * 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used * 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used @@ -196,19 +180,19 @@ typedef vtr::StrongId CircuitEdgeId; * * ------ Metal wire-related parameters ------ * Note: only applicable to circuit models whose type is wires or channel wires - * 1. wire_types_: types of the metal wire for the circuit_model + * 1. wire_types_: types of the metal wire for the model * 2. wire_res_val_: resistance value of the metal wire for the circuit model * 3. wire_cap_val_: capacitance value of the metal wire for the circuit model * 4. wire_num_levels_: number of levels of the metal wire model for the circuit model ***********************************************************************/ class CircuitLibrary { public: /* Types */ - typedef vtr::vector::const_iterator circuit_model_iterator; - typedef vtr::vector::const_iterator circuit_model_string_iterator; + typedef vtr::vector::const_iterator model_iterator; + typedef vtr::vector::const_iterator model_string_iterator; typedef vtr::vector::const_iterator circuit_port_iterator; typedef vtr::vector::const_iterator circuit_edge_iterator; /* Create range */ - typedef vtr::Range circuit_model_range; + typedef vtr::Range model_range; typedef vtr::Range circuit_port_range; typedef vtr::Range circuit_edge_range; /* local enumeration for buffer existence */ @@ -218,272 +202,272 @@ class CircuitLibrary { public: /* Constructors */ CircuitLibrary(); public: /* Accessors: aggregates */ - circuit_model_range circuit_models() const; - circuit_port_range ports(const CircuitModelId& circuit_model_id) const; - std::vector circuit_models_by_type(const enum e_spice_model_type& type) const; - std::vector ports_by_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_port_type& port_type) const; - std::vector ports_by_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; - std::vector input_ports(const CircuitModelId& circuit_model_id) const; - std::vector output_ports(const CircuitModelId& circuit_model_id) const; - std::vector pins(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + model_range models() const; + circuit_port_range ports(const CircuitModelId& model_id) const; + std::vector models_by_type(const enum e_spice_model_type& type) const; + std::vector ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type) const; + std::vector ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; + std::vector input_ports(const CircuitModelId& model_id) const; + std::vector output_ports(const CircuitModelId& model_id) const; + std::vector pins(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; public: /* Public Accessors: Basic data query on Circuit Models*/ - size_t num_circuit_models() const; - enum e_spice_model_type circuit_model_type(const CircuitModelId& circuit_model_id) const; - std::string circuit_model_name(const CircuitModelId& circuit_model_id) const; - std::string circuit_model_prefix(const CircuitModelId& circuit_model_id) const; - std::string circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id) const; - std::string circuit_model_spice_netlist(const CircuitModelId& circuit_model_id) const; - bool circuit_model_is_default(const CircuitModelId& circuit_model_id) const; - bool dump_structural_verilog(const CircuitModelId& circuit_model_id) const; - bool dump_explicit_port_map(const CircuitModelId& circuit_model_id) const; - enum e_spice_model_design_tech design_tech_type(const CircuitModelId& circuit_model_id) const; - bool is_power_gated(const CircuitModelId& circuit_model_id) const; - bool is_input_buffered(const CircuitModelId& circuit_model_id) const; - bool is_output_buffered(const CircuitModelId& circuit_model_id) const; - bool is_lut_intermediate_buffered(const CircuitModelId& circuit_model_id) const; - enum e_spice_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& circuit_model_id) const; - enum e_spice_model_structure mux_structure(const CircuitModelId& circuit_model_id) const; - size_t mux_num_levels(const CircuitModelId& circuit_model_id) const; - bool mux_add_const_input(const CircuitModelId& circuit_model_id) const; - size_t mux_const_input_value(const CircuitModelId& circuit_model_id) const; + size_t num_models() const; + enum e_spice_model_type model_type(const CircuitModelId& model_id) const; + std::string model_name(const CircuitModelId& model_id) const; + std::string model_prefix(const CircuitModelId& model_id) const; + std::string model_verilog_netlist(const CircuitModelId& model_id) const; + std::string model_spice_netlist(const CircuitModelId& model_id) const; + bool model_is_default(const CircuitModelId& model_id) const; + bool dump_structural_verilog(const CircuitModelId& model_id) const; + bool dump_explicit_port_map(const CircuitModelId& model_id) const; + enum e_spice_model_design_tech design_tech_type(const CircuitModelId& model_id) const; + bool is_power_gated(const CircuitModelId& model_id) const; + bool is_input_buffered(const CircuitModelId& model_id) const; + bool is_output_buffered(const CircuitModelId& model_id) const; + bool is_lut_intermediate_buffered(const CircuitModelId& model_id) const; + enum e_spice_model_pass_gate_logic_type pass_gate_logic_type(const CircuitModelId& model_id) const; + enum e_spice_model_structure mux_structure(const CircuitModelId& model_id) const; + size_t mux_num_levels(const CircuitModelId& model_id) const; + bool mux_add_const_input(const CircuitModelId& model_id) const; + size_t mux_const_input_value(const CircuitModelId& model_id) const; public: /* Public Accessors: Basic data query on Circuit Ports*/ - bool is_input_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool is_output_port(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - CircuitPortId port(const CircuitModelId& circuit_model_id, const std::string& name) const; - size_t num_ports(const CircuitModelId& circuit_model_id) const; - size_t num_ports_by_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; - enum e_spice_model_port_type port_type(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - size_t port_size(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - std::string port_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - std::string port_lib_name(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - std::string port_inv_prefix(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - size_t port_default_value(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_mode_select(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_global(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_reset(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_set(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_config_enable(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool port_is_prog(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; + bool is_input_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool is_output_port(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + CircuitPortId port(const CircuitModelId& model_id, const std::string& name) const; + size_t num_ports(const CircuitModelId& model_id) const; + size_t num_ports_by_type(const CircuitModelId& model_id, const enum e_spice_model_port_type& port_type, const bool& include_global_port) const; + enum e_spice_model_port_type port_type(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + size_t port_size(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + std::string port_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + std::string port_lib_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + std::string port_inv_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + size_t port_default_value(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_mode_select(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_global(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_reset(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_set(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_config_enable(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool port_is_prog(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; public: /* Public Accessors: Methods to find circuit model */ - CircuitModelId circuit_model(const char* name) const; - CircuitModelId circuit_model(const std::string& name) const; - CircuitModelId default_circuit_model(const enum e_spice_model_type& type) const; + CircuitModelId model(const char* name) const; + CircuitModelId model(const std::string& name) const; + CircuitModelId default_model(const enum e_spice_model_type& type) const; public: /* Public Accessors: Timing graph */ - CircuitEdgeId edge(const CircuitModelId& circuit_model_id, + CircuitEdgeId edge(const CircuitModelId& model_id, const CircuitPortId& from_port, const size_t from_pin, const CircuitPortId& to_port, const size_t to_pin); public: /* Public Mutators */ - CircuitModelId add_circuit_model(); + CircuitModelId add_model(); /* Fundamental information */ - void set_circuit_model_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_type& type); - void set_circuit_model_name(const CircuitModelId& circuit_model_id, const std::string& name); - void set_circuit_model_prefix(const CircuitModelId& circuit_model_id, const std::string& prefix); - void set_circuit_model_verilog_netlist(const CircuitModelId& circuit_model_id, const std::string& verilog_netlist); - void set_circuit_model_spice_netlist(const CircuitModelId& circuit_model_id, const std::string& spice_netlist); - void set_circuit_model_is_default(const CircuitModelId& circuit_model_id, const bool& is_default); + void set_model_type(const CircuitModelId& model_id, const enum e_spice_model_type& type); + void set_model_name(const CircuitModelId& model_id, const std::string& name); + void set_model_prefix(const CircuitModelId& model_id, const std::string& prefix); + void set_model_verilog_netlist(const CircuitModelId& model_id, const std::string& verilog_netlist); + void set_model_spice_netlist(const CircuitModelId& model_id, const std::string& spice_netlist); + void set_model_is_default(const CircuitModelId& model_id, const bool& is_default); /* Verilog generator options */ - void set_circuit_model_dump_structural_verilog(const CircuitModelId& circuit_model_id, const bool& dump_structural_verilog); - void set_circuit_model_dump_explicit_port_map(const CircuitModelId& circuit_model_id, const bool& dump_explicit_port_map); + void set_model_dump_structural_verilog(const CircuitModelId& model_id, const bool& dump_structural_verilog); + void set_model_dump_explicit_port_map(const CircuitModelId& model_id, const bool& dump_explicit_port_map); /* Design technology information */ - void set_circuit_model_design_tech_type(const CircuitModelId& circuit_model_id, const enum e_spice_model_design_tech& design_tech_type); - void set_circuit_model_is_power_gated(const CircuitModelId& circuit_model_id, const bool& is_power_gated); + void set_model_design_tech_type(const CircuitModelId& model_id, const enum e_spice_model_design_tech& design_tech_type); + void set_model_is_power_gated(const CircuitModelId& model_id, const bool& is_power_gated); /* Buffer existence */ - void set_circuit_model_input_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_output_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_input_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_input_inverter(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_intermediate_buffer(const CircuitModelId& circuit_model_id, - const bool& existence, const std::string& circuit_model_name); - void set_circuit_model_lut_intermediate_buffer_location_map(const CircuitModelId& circuit_model_id, + void set_model_input_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name); + void set_model_output_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name); + void set_model_lut_input_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name); + void set_model_lut_input_inverter(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name); + void set_model_lut_intermediate_buffer(const CircuitModelId& model_id, + const bool& existence, const std::string& model_name); + void set_model_lut_intermediate_buffer_location_map(const CircuitModelId& model_id, const std::string& location_map); /* Pass-gate-related parameters */ - void set_circuit_model_pass_gate_logic(const CircuitModelId& circuit_model_id, const std::string& circuit_model_name); + void set_model_pass_gate_logic(const CircuitModelId& model_id, const std::string& model_name); /* Port information */ - CircuitPortId add_circuit_model_port(const CircuitModelId& circuit_model_id); - void set_port_type(const CircuitModelId& circuit_model_id, + CircuitPortId add_model_port(const CircuitModelId& model_id); + void set_port_type(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const enum e_spice_model_port_type& port_type); - void set_port_size(const CircuitModelId& circuit_model_id, + void set_port_size(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& port_size); - void set_port_prefix(const CircuitModelId& circuit_model_id, + void set_port_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& port_prefix); - void set_port_lib_name(const CircuitModelId& circuit_model_id, + void set_port_lib_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& lib_name); - void set_port_inv_prefix(const CircuitModelId& circuit_model_id, + void set_port_inv_prefix(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& inv_prefix); - void set_port_default_value(const CircuitModelId& circuit_model_id, + void set_port_default_value(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& default_val); - void set_port_is_mode_select(const CircuitModelId& circuit_model_id, + void set_port_is_mode_select(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_mode_select); - void set_port_is_global(const CircuitModelId& circuit_model_id, + void set_port_is_global(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_global); - void set_port_is_reset(const CircuitModelId& circuit_model_id, + void set_port_is_reset(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_reset); - void set_port_is_set(const CircuitModelId& circuit_model_id, + void set_port_is_set(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_set); - void set_port_is_config_enable(const CircuitModelId& circuit_model_id, + void set_port_is_config_enable(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_config_enable); - void set_port_is_prog(const CircuitModelId& circuit_model_id, + void set_port_is_prog(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const bool& is_prog); - void set_port_circuit_model_name(const CircuitModelId& circuit_model_id, + void set_port_model_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const std::string& circuit_model_name); - void set_port_circuit_model_id(const CircuitModelId& circuit_model_id, + const std::string& model_name); + void set_port_model_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const CircuitModelId& port_circuit_model_id); - void set_port_inv_circuit_model_name(const CircuitModelId& circuit_model_id, + const CircuitModelId& port_model_id); + void set_port_inv_model_name(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const std::string& inv_circuit_model_name); - void set_port_inv_circuit_model_id(const CircuitModelId& circuit_model_id, + const std::string& inv_model_name); + void set_port_inv_model_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, - const CircuitModelId& inv_circuit_model_id); - void set_port_tri_state_map(const CircuitModelId& circuit_model_id, + const CircuitModelId& inv_model_id); + void set_port_tri_state_map(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::string& tri_state_map); - void set_port_lut_frac_level(const CircuitModelId& circuit_model_id, + void set_port_lut_frac_level(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& lut_frac_level); - void set_port_lut_output_mask(const CircuitModelId& circuit_model_id, + void set_port_lut_output_mask(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const std::vector& lut_output_masks); - void set_port_sram_orgz(const CircuitModelId& circuit_model_id, + void set_port_sram_orgz(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const enum e_sram_orgz& sram_orgz); /* Delay information */ - void add_delay_info(const CircuitModelId& circuit_model_id, + void add_delay_info(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type); - void set_delay_in_port_names(const CircuitModelId& circuit_model_id, + void set_delay_in_port_names(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type, const std::string& in_port_names); - void set_delay_out_port_names(const CircuitModelId& circuit_model_id, + void set_delay_out_port_names(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type, const std::string& out_port_names); - void set_delay_values(const CircuitModelId& circuit_model_id, + void set_delay_values(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type, const std::string& delay_values); /* Buffer/Inverter-related parameters */ - void set_buffer_type(const CircuitModelId& circuit_model_id, + void set_buffer_type(const CircuitModelId& model_id, const enum e_spice_model_buffer_type& buffer_type); - void set_buffer_size(const CircuitModelId& circuit_model_id, + void set_buffer_size(const CircuitModelId& model_id, const float& buffer_size); - void set_buffer_num_levels(const CircuitModelId& circuit_model_id, + void set_buffer_num_levels(const CircuitModelId& model_id, const size_t& num_levels); - void set_buffer_f_per_stage(const CircuitModelId& circuit_model_id, + void set_buffer_f_per_stage(const CircuitModelId& model_id, const size_t& f_per_stage); /* Pass-gate-related parameters */ - void set_pass_gate_logic_type(const CircuitModelId& circuit_model_id, + void set_pass_gate_logic_type(const CircuitModelId& model_id, const enum e_spice_model_pass_gate_logic_type& pass_gate_logic_type); - void set_pass_gate_logic_nmos_size(const CircuitModelId& circuit_model_id, + void set_pass_gate_logic_nmos_size(const CircuitModelId& model_id, const float& nmos_size); - void set_pass_gate_logic_pmos_size(const CircuitModelId& circuit_model_id, + void set_pass_gate_logic_pmos_size(const CircuitModelId& model_id, const float& pmos_size); /* Multiplexer-related parameters */ - void set_mux_structure(const CircuitModelId& circuit_model_id, + void set_mux_structure(const CircuitModelId& model_id, const enum e_spice_model_structure& mux_structure); - void set_mux_num_levels(const CircuitModelId& circuit_model_id, + void set_mux_num_levels(const CircuitModelId& model_id, const size_t& num_levels); - void set_mux_const_input_value(const CircuitModelId& circuit_model_id, + void set_mux_const_input_value(const CircuitModelId& model_id, const size_t& const_input_value); - void set_mux_use_local_encoder(const CircuitModelId& circuit_model_id, + void set_mux_use_local_encoder(const CircuitModelId& model_id, const bool& use_local_encoder); - void set_mux_use_advanced_rram_design(const CircuitModelId& circuit_model_id, + void set_mux_use_advanced_rram_design(const CircuitModelId& model_id, const bool& use_advanced_rram_design); /* LUT-related parameters */ - void set_lut_is_fracturable(const CircuitModelId& circuit_model_id, + void set_lut_is_fracturable(const CircuitModelId& model_id, const bool& is_fracturable); /* Gate-related parameters */ - void set_gate_type(const CircuitModelId& circuit_model_id, + void set_gate_type(const CircuitModelId& model_id, const enum e_spice_model_gate_type& gate_type); /* RRAM-related design technology information */ - void set_rram_rlrs(const CircuitModelId& circuit_model_id, + void set_rram_rlrs(const CircuitModelId& model_id, const float& rlrs); - void set_rram_rhrs(const CircuitModelId& circuit_model_id, + void set_rram_rhrs(const CircuitModelId& model_id, const float& rhrs); - void set_rram_wprog_set_nmos(const CircuitModelId& circuit_model_id, + void set_rram_wprog_set_nmos(const CircuitModelId& model_id, const float& wprog_set_nmos); - void set_rram_wprog_set_pmos(const CircuitModelId& circuit_model_id, + void set_rram_wprog_set_pmos(const CircuitModelId& model_id, const float& wprog_set_pmos); - void set_rram_wprog_reset_nmos(const CircuitModelId& circuit_model_id, + void set_rram_wprog_reset_nmos(const CircuitModelId& model_id, const float& wprog_reset_nmos); - void set_rram_wprog_reset_pmos(const CircuitModelId& circuit_model_id, + void set_rram_wprog_reset_pmos(const CircuitModelId& model_id, const float& wprog_reset_pmos); /* Wire parameters */ - void set_wire_type(const CircuitModelId& circuit_model_id, + void set_wire_type(const CircuitModelId& model_id, const enum e_wire_model_type& wire_type); - void set_wire_r(const CircuitModelId& circuit_model_id, + void set_wire_r(const CircuitModelId& model_id, const float& r_val); - void set_wire_c(const CircuitModelId& circuit_model_id, + void set_wire_c(const CircuitModelId& model_id, const float& c_val); - void set_wire_num_levels(const CircuitModelId& circuit_model_id, + void set_wire_num_levels(const CircuitModelId& model_id, const size_t& num_level); public: /* Public Mutators: builders */ - void set_circuit_model_buffer(const CircuitModelId& circuit_model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& circuit_model_name); - void link_port_circuit_model(const CircuitModelId& circuit_model_id); - void link_port_inv_circuit_model(const CircuitModelId& circuit_model_id); - void link_port_circuit_models(const CircuitModelId& circuit_model_id); - void link_buffer_circuit_model(const CircuitModelId& circuit_model_id); - void link_pass_gate_logic_circuit_model(const CircuitModelId& circuit_model_id); - void build_circuit_model_links(); - void build_circuit_model_timing_graph(const CircuitModelId& circuit_model_id); + void set_model_buffer(const CircuitModelId& model_id, const enum e_buffer_type buffer_type, const bool& existence, const std::string& model_name); + void link_port_model(const CircuitModelId& model_id); + void link_port_inv_model(const CircuitModelId& model_id); + void link_port_models(const CircuitModelId& model_id); + void link_buffer_model(const CircuitModelId& model_id); + void link_pass_gate_logic_model(const CircuitModelId& model_id); + void build_model_links(); + void build_model_timing_graph(const CircuitModelId& model_id); void build_timing_graphs(); public: /* Internal mutators: build timing graphs */ - void add_edge(const CircuitModelId& circuit_model_id, + void add_edge(const CircuitModelId& model_id, const CircuitPortId& from_port, const size_t& from_pin, const CircuitPortId& to_port, const size_t& to_pin); - void set_edge_delay(const CircuitModelId& circuit_model_id, + void set_edge_delay(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id, const enum spice_model_delay_type& delay_type, const float& delay_value); /* validate the circuit_edge_id */ - void set_timing_graph_delays(const CircuitModelId& circuit_model_id); + void set_timing_graph_delays(const CircuitModelId& model_id); public: /* Internal mutators: build fast look-ups */ - void build_circuit_model_lookup(); - void build_circuit_model_port_lookup(const CircuitModelId& circuit_model_id); + void build_model_lookup(); + void build_model_port_lookup(const CircuitModelId& model_id); private: /* Internal invalidators/validators */ /* Validators */ - bool valid_circuit_model_id(const CircuitModelId& circuit_model_id) const; - bool valid_circuit_port_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id) const; - bool valid_circuit_pin_id(const CircuitModelId& circuit_model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const; - bool valid_delay_type(const CircuitModelId& circuit_model_id, const enum spice_model_delay_type& delay_type) const; - bool valid_circuit_edge_id(const CircuitModelId& circuit_model_id, const CircuitEdgeId& circuit_edge_id) const; + bool valid_model_id(const CircuitModelId& model_id) const; + bool valid_circuit_port_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id) const; + bool valid_circuit_pin_id(const CircuitModelId& model_id, const CircuitPortId& circuit_port_id, const size_t& pin_id) const; + bool valid_delay_type(const CircuitModelId& model_id, const enum spice_model_delay_type& delay_type) const; + bool valid_circuit_edge_id(const CircuitModelId& model_id, const CircuitEdgeId& circuit_edge_id) const; bool valid_mux_const_input_value(const size_t& const_input_value) const; /* Invalidators */ - void invalidate_circuit_model_lookup() const; - void invalidate_circuit_model_port_lookup(const CircuitModelId& circuit_model_id) const; - void invalidate_circuit_model_timing_graph(const CircuitModelId& circuit_model_id); + void invalidate_model_lookup() const; + void invalidate_model_port_lookup(const CircuitModelId& model_id) const; + void invalidate_model_timing_graph(const CircuitModelId& model_id); private: /* Internal data */ /* Fundamental information */ - vtr::vector circuit_model_ids_; - vtr::vector circuit_model_types_; - vtr::vector circuit_model_names_; - vtr::vector circuit_model_prefix_; - vtr::vector circuit_model_verilog_netlists_; - vtr::vector circuit_model_spice_netlists_; - vtr::vector circuit_model_is_default_; + vtr::vector model_ids_; + vtr::vector model_types_; + vtr::vector model_names_; + vtr::vector model_prefix_; + vtr::vector model_verilog_netlists_; + vtr::vector model_spice_netlists_; + vtr::vector model_is_default_; /* fast look-up for circuit models to categorize by types * [type][num_ids] * Important: we force the default circuit model in the first element for each type */ typedef std::vector> CircuitModelLookup; - mutable CircuitModelLookup circuit_model_lookup_; /* [circuit_model_type][circuit_model_ids] */ + mutable CircuitModelLookup model_lookup_; /* [model_type][model_ids] */ typedef std::vector>> CircuitModelPortLookup; - mutable CircuitModelPortLookup circuit_model_port_lookup_; /* [circuit_model_id][port_type][port_ids] */ + mutable CircuitModelPortLookup model_port_lookup_; /* [model_id][port_type][port_ids] */ /* Verilog generator options */ vtr::vector dump_structural_verilog_; @@ -495,13 +479,13 @@ class CircuitLibrary { /* Buffer existence */ vtr::vector> buffer_existence_; - vtr::vector> buffer_circuit_model_names_; - vtr::vector> buffer_circuit_model_ids_; + vtr::vector> buffer_model_names_; + vtr::vector> buffer_model_ids_; vtr::vector> buffer_location_maps_; /* Pass-gate-related parameters */ - vtr::vector pass_gate_logic_circuit_model_names_; - vtr::vector pass_gate_logic_circuit_model_ids_; + vtr::vector pass_gate_logic_model_names_; + vtr::vector pass_gate_logic_model_ids_; /* Port information */ vtr::vector> port_ids_; @@ -517,10 +501,10 @@ class CircuitLibrary { vtr::vector> port_is_set_; vtr::vector> port_is_config_enable_; vtr::vector> port_is_prog_; - vtr::vector> port_circuit_model_names_; - vtr::vector> port_circuit_model_ids_; - vtr::vector> port_inv_circuit_model_names_; - vtr::vector> port_inv_circuit_model_ids_; + vtr::vector> port_model_names_; + vtr::vector> port_model_ids_; + vtr::vector> port_inv_model_names_; + vtr::vector> port_inv_model_ids_; vtr::vector> port_tri_state_maps_; vtr::vector> port_lut_frac_level_; vtr::vector>> port_lut_output_masks_; diff --git a/vpr7_x2p/libarchfpga/SRC/circuit_library_fwd.h b/vpr7_x2p/libarchfpga/SRC/circuit_library_fwd.h new file mode 100644 index 000000000..522fbbfcc --- /dev/null +++ b/vpr7_x2p/libarchfpga/SRC/circuit_library_fwd.h @@ -0,0 +1,21 @@ +/************************************************************************ + * A header file for CircuitLibrary class, including critical data declaration + * Please include this file only for using any CircuitLibrary data structure + * Refer to circuit_library.h for more details + ***********************************************************************/ + +/************************************************************************ + * Create strong id for Circuit Models/Ports to avoid illegal type casting + ***********************************************************************/ +#include "vtr_strong_id.h" + +struct circuit_model_id_tag; +struct circuit_port_id_tag; +struct circuit_edge_id_tag; + +typedef vtr::StrongId CircuitModelId; +typedef vtr::StrongId CircuitPortId; +typedef vtr::StrongId CircuitEdgeId; + +/* Short declaration of class */ +class CircuitLibrary; diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index 17ebb718a..e6f400fb2 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -1573,38 +1573,38 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m /* Go spice_model by spice_model */ for (int imodel = 0; imodel < num_spice_model; ++imodel) { /* Add a spice model to the circuit_lib */ - CircuitModelId model_id = circuit_lib.add_circuit_model(); + CircuitModelId model_id = circuit_lib.add_model(); /* Fill fundamental attributes */ /* Basic information*/ - circuit_lib.set_circuit_model_type(model_id, spice_models[imodel].type); + circuit_lib.set_model_type(model_id, spice_models[imodel].type); std::string name(spice_models[imodel].name); - circuit_lib.set_circuit_model_name(model_id, name); + circuit_lib.set_model_name(model_id, name); std::string prefix(spice_models[imodel].prefix); - circuit_lib.set_circuit_model_prefix(model_id, prefix); + circuit_lib.set_model_prefix(model_id, prefix); if (NULL != spice_models[imodel].verilog_netlist) { std::string verilog_netlist(spice_models[imodel].verilog_netlist); - circuit_lib.set_circuit_model_verilog_netlist(model_id, verilog_netlist); + circuit_lib.set_model_verilog_netlist(model_id, verilog_netlist); } if (NULL != spice_models[imodel].model_netlist) { std::string spice_netlist(spice_models[imodel].model_netlist); - circuit_lib.set_circuit_model_spice_netlist(model_id, spice_netlist); + circuit_lib.set_model_spice_netlist(model_id, spice_netlist); } - circuit_lib.set_circuit_model_is_default(model_id, 0 != spice_models[imodel].is_default); + circuit_lib.set_model_is_default(model_id, 0 != spice_models[imodel].is_default); /* Verilog generatioin options */ - circuit_lib.set_circuit_model_dump_structural_verilog(model_id, TRUE == spice_models[imodel].dump_structural_verilog); + circuit_lib.set_model_dump_structural_verilog(model_id, TRUE == spice_models[imodel].dump_structural_verilog); - circuit_lib.set_circuit_model_dump_explicit_port_map(model_id, TRUE == spice_models[imodel].dump_explicit_port_map); + circuit_lib.set_model_dump_explicit_port_map(model_id, TRUE == spice_models[imodel].dump_explicit_port_map); /* Design technology information */ - circuit_lib.set_circuit_model_design_tech_type(model_id, spice_models[imodel].design_tech); + circuit_lib.set_model_design_tech_type(model_id, spice_models[imodel].design_tech); - circuit_lib.set_circuit_model_is_power_gated(model_id, TRUE == spice_models[imodel].design_tech_info.power_gated); + circuit_lib.set_model_is_power_gated(model_id, TRUE == spice_models[imodel].design_tech_info.power_gated); /* Buffer linking information */ if (NULL != spice_models[imodel].input_buffer) { @@ -1612,28 +1612,28 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m if (NULL != spice_models[imodel].input_buffer->spice_model_name) { model_name = spice_models[imodel].input_buffer->spice_model_name; } - circuit_lib.set_circuit_model_input_buffer(model_id, 0 != spice_models[imodel].input_buffer->exist, model_name); + circuit_lib.set_model_input_buffer(model_id, 0 != spice_models[imodel].input_buffer->exist, model_name); } if (NULL != spice_models[imodel].output_buffer) { std::string model_name; if (NULL != spice_models[imodel].output_buffer->spice_model_name) { model_name = spice_models[imodel].output_buffer->spice_model_name; } - circuit_lib.set_circuit_model_output_buffer(model_id, 0 != spice_models[imodel].output_buffer->exist, model_name); + circuit_lib.set_model_output_buffer(model_id, 0 != spice_models[imodel].output_buffer->exist, model_name); } if (NULL != spice_models[imodel].lut_input_buffer) { std::string model_name; if (NULL != spice_models[imodel].lut_input_buffer->spice_model_name) { model_name = spice_models[imodel].lut_input_buffer->spice_model_name; } - circuit_lib.set_circuit_model_lut_input_buffer(model_id, 0 != spice_models[imodel].lut_input_buffer->exist, model_name); + circuit_lib.set_model_lut_input_buffer(model_id, 0 != spice_models[imodel].lut_input_buffer->exist, model_name); } if (NULL != spice_models[imodel].lut_input_inverter) { std::string model_name; if (NULL != spice_models[imodel].lut_input_inverter->spice_model_name) { model_name = spice_models[imodel].lut_input_inverter->spice_model_name; } - circuit_lib.set_circuit_model_lut_input_inverter(model_id, 0 != spice_models[imodel].lut_input_inverter->exist, model_name); + circuit_lib.set_model_lut_input_inverter(model_id, 0 != spice_models[imodel].lut_input_inverter->exist, model_name); } if ( (NULL != spice_models[imodel].lut_intermediate_buffer) && (1 == spice_models[imodel].lut_intermediate_buffer->exist) ) { @@ -1641,19 +1641,19 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m if (NULL != spice_models[imodel].lut_intermediate_buffer->spice_model_name) { model_name = spice_models[imodel].lut_intermediate_buffer->spice_model_name; } - circuit_lib.set_circuit_model_lut_intermediate_buffer(model_id, 0 != spice_models[imodel].lut_intermediate_buffer->exist, model_name); + circuit_lib.set_model_lut_intermediate_buffer(model_id, 0 != spice_models[imodel].lut_intermediate_buffer->exist, model_name); std::string model_location_map; if (NULL != spice_models[imodel].lut_intermediate_buffer->location_map) { model_location_map = spice_models[imodel].lut_intermediate_buffer->location_map; } - circuit_lib.set_circuit_model_lut_intermediate_buffer_location_map(model_id, model_location_map); + circuit_lib.set_model_lut_intermediate_buffer_location_map(model_id, model_location_map); } /* Pass-gate-logic linking information */ if (NULL != spice_models[imodel].pass_gate_logic) { std::string model_name(spice_models[imodel].pass_gate_logic->spice_model_name); - circuit_lib.set_circuit_model_pass_gate_logic(model_id, model_name); + circuit_lib.set_model_pass_gate_logic(model_id, model_name); } /* Buffer information */ @@ -1728,7 +1728,7 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m /* Ports */ for (int iport = 0; iport < spice_models[imodel].num_port; ++iport) { - CircuitPortId port_id = circuit_lib.add_circuit_model_port(model_id); + CircuitPortId port_id = circuit_lib.add_model_port(model_id); /* Fill fundamental attributes */ circuit_lib.set_port_type(model_id, port_id, spice_models[imodel].ports[iport].type); @@ -1756,12 +1756,12 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m if (NULL != spice_models[imodel].ports[iport].spice_model_name) { std::string port_model_name(spice_models[imodel].ports[iport].spice_model_name); - circuit_lib.set_port_circuit_model_name(model_id, port_id, port_model_name); + circuit_lib.set_port_model_name(model_id, port_id, port_model_name); } if (NULL != spice_models[imodel].ports[iport].inv_spice_model_name) { std::string port_inv_model_name(spice_models[imodel].ports[iport].inv_spice_model_name); - circuit_lib.set_port_inv_circuit_model_name(model_id, port_id, port_inv_model_name); + circuit_lib.set_port_inv_model_name(model_id, port_id, port_inv_model_name); } if (NULL != spice_models[imodel].ports[iport].tri_state_map) { @@ -1786,7 +1786,7 @@ CircuitLibrary build_circuit_library(int num_spice_model, t_spice_model* spice_m } /* Build circuit_model links */ - circuit_lib.build_circuit_model_links(); + circuit_lib.build_model_links(); /* Build timing graph */ circuit_lib.build_timing_graphs(); diff --git a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp index 30a4c9b51..1312384c1 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_graph.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_graph.cpp @@ -553,8 +553,8 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model, const size_t& mux_size) { /* Make sure this model is a MUX */ - VTR_ASSERT((SPICE_MODEL_MUX == circuit_lib.circuit_model_type(circuit_model)) - || (SPICE_MODEL_LUT == circuit_lib.circuit_model_type(circuit_model)) ); + VTR_ASSERT((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) + || (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) ); /* Make sure mux_size is valid */ VTR_ASSERT(valid_mux_implementation_num_inputs(mux_size)); @@ -594,7 +594,7 @@ void MuxGraph::build_mux_graph(const CircuitLibrary& circuit_lib, default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d]) Invalid multiplexer structure for circuit model (name=%s)!\n", - __FILE__, __LINE__, circuit_lib.circuit_model_name(circuit_model)); + __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); exit(1); } diff --git a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp index 29cb0e5ec..f7eb9932c 100644 --- a/vpr7_x2p/vpr/SRC/device/mux_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/mux_utils.cpp @@ -28,10 +28,10 @@ size_t find_mux_implementation_num_inputs(const CircuitLibrary& circuit_lib, /* Should be either MUX or LUT * LUTs do have an tree-like MUX, but there is no need for a constant input! */ - VTR_ASSERT ((SPICE_MODEL_MUX == circuit_lib.circuit_model_type(circuit_model)) - || (SPICE_MODEL_LUT == circuit_lib.circuit_model_type(circuit_model)) ); + VTR_ASSERT ((SPICE_MODEL_MUX == circuit_lib.model_type(circuit_model)) + || (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) ); - if (SPICE_MODEL_LUT == circuit_lib.circuit_model_type(circuit_model)) { + if (SPICE_MODEL_LUT == circuit_lib.model_type(circuit_model)) { return mux_size; } @@ -147,7 +147,7 @@ MuxLibrary convert_mux_arch_to_library(const CircuitLibrary& circuit_lib, t_llis /* Build a MUX graph for the model */ /* Find the circuit model id by the name */ - CircuitModelId circuit_model = circuit_lib.circuit_model(cur_spice_mux_model->spice_model->name); + CircuitModelId circuit_model = circuit_lib.model(cur_spice_mux_model->spice_model->name); mux_lib.add_mux(circuit_lib, circuit_model, cur_spice_mux_model->size); /* Move on to the next*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp index 3cdd35eb1..c8dd0b8c3 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/link_arch_circuit_lib.cpp @@ -81,31 +81,31 @@ CircuitModelId link_circuit_model_by_name_and_type(const char* circuit_model_name, const CircuitLibrary& circuit_lib, const enum e_spice_model_type& model_type) { - CircuitModelId circuit_model = CIRCUIT_MODEL_OPEN_ID; + CircuitModelId circuit_model = CircuitModelId::INVALID(); /* If the circuit_model_name is not defined, we use the default*/ if (NULL == circuit_model_name) { - circuit_model = circuit_lib.default_circuit_model(model_type); + circuit_model = circuit_lib.default_model(model_type); } else { - circuit_model = circuit_lib.circuit_model(circuit_model_name); + circuit_model = circuit_lib.model(circuit_model_name); } /* Check the circuit model, we should have one! */ - if (CIRCUIT_MODEL_OPEN_ID == circuit_model) { + if (CircuitModelId::INVALID() == circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Fail to find a defined circuit model called %s!\n", __FILE__, __LINE__, - circuit_lib.circuit_model_name(circuit_model).c_str()); + circuit_lib.model_name(circuit_model).c_str()); return circuit_model; /* Return here, no need to check the model_type */ } /* Check the type of circuit model, make sure it is the one we want */ - if (model_type != circuit_lib.circuit_model_type(circuit_model)) { + if (model_type != circuit_lib.model_type(circuit_model)) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Invalid type when trying to find circuit model called %s! Expect %s but found %s!\n", __FILE__, __LINE__, circuit_model_name, CIRCUIT_MODEL_TYPE_STRING[size_t(model_type)], - CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.circuit_model_type(circuit_model))]); + CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))]); } return circuit_model; @@ -267,11 +267,11 @@ int link_pb_type_port_to_circuit_model_ports(const t_pb_type* cur_pb_type, /* Initialize each port */ for (int iport = 0; iport < cur_pb_type->num_ports; iport++) { - cur_pb_type->ports[iport].circuit_model_port = CIRCUIT_PORT_OPEN_ID; + cur_pb_type->ports[iport].circuit_model_port = CircuitPortId::INVALID(); } /* Return if SPICE_MODEL is NULL */ - if (CIRCUIT_MODEL_OPEN_ID == circuit_model) { + if (CircuitModelId::INVALID() == circuit_model) { return 0; } @@ -290,11 +290,11 @@ int link_pb_type_port_to_circuit_model_ports(const t_pb_type* cur_pb_type, * but each pb_type_port should be mapped to a spice_model_port */ for (int iport = 0; iport < cur_pb_type->num_ports; iport++) { - if (CIRCUIT_PORT_OPEN_ID == cur_pb_type->ports[iport].circuit_model_port) { + if (CircuitPortId::INVALID() == cur_pb_type->ports[iport].circuit_model_port) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Pb_type(%s) Port(%s) cannot find a corresponding port in SPICE model(%s)\n", __FILE__, __LINE__, cur_pb_type->name, cur_pb_type->ports[iport].name, - circuit_lib.circuit_model_name(circuit_model).c_str()); + circuit_lib.model_name(circuit_model).c_str()); exit(1); } } @@ -319,7 +319,7 @@ void link_pb_type_interc_circuit_model_by_type(t_interconnect* cur_interc, circuit_lib, model_type); /* Check the circuit model, we should have one! */ - if (CIRCUIT_MODEL_OPEN_ID == cur_interc->circuit_model) { + if (CircuitModelId::INVALID() == cur_interc->circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Error in linking circuit model for interconnect(name %s)! Check [LINE%d] in architecture file)!\n", __FILE__, __LINE__, @@ -415,8 +415,8 @@ void link_pb_types_circuit_model_rec(t_pb_type* cur_pb_type, return; } /* Let's find a matched circuit model!*/ - cur_pb_type->circuit_model = circuit_lib.circuit_model(cur_pb_type->spice_model_name); - if (CIRCUIT_MODEL_OPEN_ID == cur_pb_type->circuit_model) { + cur_pb_type->circuit_model = circuit_lib.model(cur_pb_type->spice_model_name); + if (CircuitModelId::INVALID() == cur_pb_type->circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,LINE[%d]) Fail to find a defined circuit model called %s, in pb_type(%s)!\n", __FILE__, __LINE__, cur_pb_type->spice_model_name, cur_pb_type->name); @@ -428,14 +428,14 @@ void link_pb_types_circuit_model_rec(t_pb_type* cur_pb_type, } /* Otherwise, initialize it to be OPEN node */ - cur_pb_type->circuit_model = CIRCUIT_MODEL_OPEN_ID; + cur_pb_type->circuit_model = CircuitModelId::INVALID(); /* Traversal the hierarchy*/ for (int imode = 0; imode < cur_pb_type->num_modes; imode++) { /* Task 1: Find the interconnections and match the spice_model */ for (int jinterc = 0; jinterc < cur_pb_type->modes[imode].num_interconnect; jinterc++) { /* Initialize it to be OPEN node */ - cur_pb_type->modes[imode].interconnect[jinterc].circuit_model = CIRCUIT_MODEL_OPEN_ID; + cur_pb_type->modes[imode].interconnect[jinterc].circuit_model = CircuitModelId::INVALID(); link_pb_type_interc_circuit_model(&(cur_pb_type->modes[imode].interconnect[jinterc]), circuit_lib); } @@ -453,12 +453,12 @@ size_t check_circuit_model_structure_match_switch_inf(const t_switch_inf& target const CircuitLibrary& circuit_lib) { size_t num_err = 0; - VTR_ASSERT_SAFE(CIRCUIT_MODEL_OPEN_ID != target_switch_inf.circuit_model); + VTR_ASSERT_SAFE(CircuitModelId::INVALID() != target_switch_inf.circuit_model); if (target_switch_inf.structure != circuit_lib.mux_structure(target_switch_inf.circuit_model)) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d]) Mismatch in MUX structure between circuit model(%s, %s) and switch_inf(%s, %s)!\n", __FILE__, __LINE__, - circuit_lib.circuit_model_name(target_switch_inf.circuit_model).c_str(), + circuit_lib.model_name(target_switch_inf.circuit_model).c_str(), CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[size_t(circuit_lib.mux_structure(target_switch_inf.circuit_model))], target_switch_inf.name, CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[size_t(target_switch_inf.structure)]); @@ -494,7 +494,7 @@ void link_circuit_library_to_arch(t_arch* arch, for (int i = 0; i < arch->num_cb_switch; i++) { arch->cb_switches[i].circuit_model = link_circuit_model_by_name_and_type(arch->cb_switches[i].spice_model_name, arch->spice->circuit_lib, SPICE_MODEL_MUX); - if (CIRCUIT_MODEL_OPEN_ID == arch->cb_switches[i].circuit_model) { + if (CircuitModelId::INVALID() == arch->cb_switches[i].circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", __FILE__, __LINE__, arch->cb_switches[i].spice_model_name, arch->cb_switches[i].name); @@ -517,7 +517,7 @@ void link_circuit_library_to_arch(t_arch* arch, for (int i = 0; i < arch->num_switches; i++) { arch->Switches[i].circuit_model = link_circuit_model_by_name_and_type(arch->Switches[i].spice_model_name, arch->spice->circuit_lib, SPICE_MODEL_MUX); - if (CIRCUIT_MODEL_OPEN_ID == arch->Switches[i].circuit_model) { + if (CircuitModelId::INVALID() == arch->Switches[i].circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", __FILE__, __LINE__, arch->Switches[i].spice_model_name, arch->Switches[i].name); @@ -533,7 +533,7 @@ void link_circuit_library_to_arch(t_arch* arch, for (int i = 0; i < routing_arch->num_switch; i++) { switch_inf[i].circuit_model = link_circuit_model_by_name_and_type(switch_inf[i].spice_model_name, arch->spice->circuit_lib, SPICE_MODEL_MUX); - if (CIRCUIT_MODEL_OPEN_ID == switch_inf[i].circuit_model) { + if (CircuitModelId::INVALID() == switch_inf[i].circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Switch(%s) is undefined in circuit models!\n", __FILE__, __LINE__, switch_inf[i].spice_model_name, switch_inf[i].name); @@ -548,7 +548,7 @@ void link_circuit_library_to_arch(t_arch* arch, for (int i = 0; i < arch->num_segments; i++) { arch->Segments[i].circuit_model = link_circuit_model_by_name_and_type(arch->Segments[i].spice_model_name, arch->spice->circuit_lib, SPICE_MODEL_CHAN_WIRE); - if (CIRCUIT_MODEL_OPEN_ID == arch->Segments[i].circuit_model) { + if (CircuitModelId::INVALID() == arch->Segments[i].circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of Segment(Length:%d) is undefined in circuit models!\n", __FILE__ ,__LINE__, @@ -563,7 +563,7 @@ void link_circuit_library_to_arch(t_arch* arch, arch->Directs[i].circuit_model = link_circuit_model_by_name_and_type(arch->Directs[i].spice_model_name, arch->spice->circuit_lib, SPICE_MODEL_WIRE); /* Check SPICE model type */ - if (CIRCUIT_MODEL_OPEN_ID == arch->Directs[i].circuit_model) { + if (CircuitModelId::INVALID() == arch->Directs[i].circuit_model) { vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s, LINE[%d])Invalid circuit model name(%s) of CLB to CLB Direct Connection (name=%s) is undefined in circuit models!\n", __FILE__ ,__LINE__, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp index e5fe1cc66..f60cef851 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_mux.cpp @@ -64,7 +64,7 @@ void generate_verilog_mux_branch_module(std::fstream& fp, default: vpr_printf(TIO_MESSAGE_ERROR, "(FILE:%s,LINE[%d]) Invalid design technology of multiplexer (name: %s)\n", - __FILE__, __LINE__, circuit_lib.circuit_model_name(circuit_model)); + __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); exit(1); }