[test] add a new testcase to validate perimeter cb

openfpga_flow/regression_test_scripts/basic_reg_test.sh

@@ -190,6 +190,8 @@ run-task basic_tests/tile_organization/tileable_io $@
 echo -e "Testing tiles with I/O consisting of subtiles";
 run-task basic_tests/tile_organization/io_subtile $@
 run-task basic_tests/tile_organization/io_subtile_strong $@
+echo -e "Testing tiles with routing tracks around I/O";
+run-task basic_tests/tile_organization/perimeter_cb $@
 echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)";
 run-task basic_tests/tile_organization/homo_fabric_tile $@
 echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)";

openfpga_flow/tasks/basic_tests/tile_organization/perimeter_cb/config/task.conf

@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_IoSubtile_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=3x3
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_IoSubtile_PerimeterCb_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = or2
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

openfpga_flow/vpr_arch/README.md

@@ -23,6 +23,7 @@ Please reveal the following architecture features in the names to help quickly s
 - reduced\_io: If I/Os only appear a certain or multiple sides of FPGAs 
 - registerable\_io: If I/Os are registerable (can be either combinational or sequential)
 - IoSubtile: If I/O block contains sub tiles (more compact with a higher density of I/Os)
+- PerimeterCb: If connection blocks can occur on perimeter I/Os (I/O tile has more routability)
 - CustomIoLoc: Use OpenFPGA's extended custom I/O location syntax
 - rstOnLut: The reset signal of CLB can feed LUT inputs through a local routing architecture
 - localClkGen: The clock signal of CLB can be generated by internal programmable resources