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[HDL] Now dual-clock counter has only 1 reset pin

This commit is contained in:
tangxifan 2022-02-15 16:07:50 -08:00
parent f002c79a61
commit a7786efde1
1 changed files with 3 additions and 4 deletions
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7
openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v
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@ -1,12 +1,11 @@
module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1); module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
input clk0; input clk0;
input rst0; input rst;
output [3:0] q0; output [3:0] q0;
reg [3:0] q0; reg [3:0] q0;
input clk1; input clk1;
input rst1;
output [3:0] q1; output [3:0] q1;
reg [3:0] q1; reg [3:0] q1;
@ -17,7 +16,7 @@ module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
always @ (posedge clk0) always @ (posedge clk0)
begin begin
if(rst0) if(rst)
q0 <= 4'b0000; q0 <= 4'b0000;
else else
q0 <= q0 + 1; q0 <= q0 + 1;
@ -25,7 +24,7 @@ module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1);
always @ (posedge clk1) always @ (posedge clk1)
begin begin
if(rst1) if(rst)
q1 <= 4'b0000; q1 <= 4'b0000;
else else
q1 <= q1 + 1; q1 <= q1 + 1;