Update architecture
This commit is contained in:
Ganesh Gore
parent
1fca83f9c7
commit
a71d5d3606
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@ -1,11 +1,3 @@
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k6_N10_40nm.xml
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- General purpose logic block
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- K = 6, N = 10, I = 40
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- Single mode
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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@ -157,21 +149,18 @@
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<segment name="L4" circuit_model_name="chan_segment"/>
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</routing_segment>
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<pb_type_annotations>
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<!-- physical pb_type binding in complex block IO -->
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<pb_type name="clb">
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<interconnect name="crossbar" circuit_model_name="mux_2level"/>
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</pb_type>
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<pb_type name="clb.fle" physical_mode_name="physical"/>
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<pb_type name="clb.fle[physical].ble6.lut6" circuit_model_name="lut6"/>
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<pb_type name="clb.fle[physical].ble6.ff" circuit_model_name="DFFSRQ"/>
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<pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].ble6.lut6"/>
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<pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].ble6.ff"/>
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<pb_type name="io" physical_mode_name="physical"/>
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<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
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<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
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<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
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<!-- End physical pb_type binding in complex block IO -->
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<!-- physical pb_type binding in complex block CLB -->
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<!-- physical mode will be the default mode if not specified -->
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<pb_type name="clb">
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<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
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<interconnect name="crossbar" circuit_model_name="mux_2level"/>
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</pb_type>
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<pb_type name="clb.fle[n1_lut6].ble6.lut6" circuit_model_name="lut6"/>
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<pb_type name="clb.fle[n1_lut6].ble6.ff" circuit_model_name="DFFSRQ"/>
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<!-- End physical pb_type binding in complex block IO -->
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</pb_type_annotations>
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</openfpga_architecture>
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@ -1,199 +1,226 @@
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<?xml version="1.0" ?><!--
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Architecture with no fracturable LUTs
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- 40 nm technology
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- General purpose logic block:
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K = 6, N = 10
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- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
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Details on Modelling:
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Based on flagship k6_frac_N10_mem32K_40nm.xml architecture. This architecture has no fracturable LUTs nor any heterogeneous blocks.
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Authors: Jason Luu, Jeff Goeders, Vaughn Betz
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--><architecture>
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<models>
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<!-- A virtual model for I/O to be used in the physical mode of io block -->
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<model name="io">
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<input_ports>
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<port name="outpad"/>
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</input_ports>
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<output_ports>
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<port name="inpad"/>
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</output_ports>
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</model>
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</models>
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<tiles>
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<tile name="io" area="0"> <sub_tile name="io" capacity="8">
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<equivalent_sites>
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<site pb_type="io"/>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="custom">
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<loc side="left">io.outpad io.inpad</loc>
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<loc side="top">io.outpad io.inpad</loc>
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<loc side="right">io.outpad io.inpad</loc>
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<loc side="bottom">io.outpad io.inpad</loc>
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</pinlocations>
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</sub_tile> </tile>
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<tile name="clb" area="53894"> <sub_tile name="clb">
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<equivalent_sites>
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<site pb_type="clb"/>
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</equivalent_sites>
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<input name="I" num_pins="40" equivalent="full"/>
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<output name="O" num_pins="10" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="spread"/>
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</sub_tile> </tile>
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</tiles>
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
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<layout tileable="true">
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<auto_layout aspect_ratio="1.0">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</auto_layout>
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</layout>
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<device>
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<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
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<area grid_logic_tile_area="0"/>
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<chan_width_distr>
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<x distr="uniform" peak="1.000000"/>
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<switch_block type="wilton" fs="3"/>
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<connection_block input_switch_name="ipin_cblock"/>
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</device>
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<switchlist>
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<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
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</switchlist>
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<segmentlist>
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<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
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<mux name="0"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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</segment>
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</segmentlist>
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<complexblocklist>
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<pb_type name="io">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<mode name="physical" disable_packing="true">
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<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="iopad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
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</direct>
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<direct name="inpad" input="iopad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="inpad">
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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</direct>
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</interconnect>
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</mode>
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<power method="ignore"/>
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</pb_type>
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<pb_type name="clb">
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<input name="I" num_pins="40" equivalent="full"/>
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<output name="O" num_pins="10" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<!-- Describe basic logic element.
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Each basic logic element has a 6-LUT that can be optionally registered
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-->
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<pb_type name="fle" num_pb="10">
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<input name="in" num_pins="6"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- 6-LUT mode definition begin -->
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<mode name="n1_lut6">
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<!-- Define 6-LUT mode -->
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<pb_type name="ble6" num_pb="1">
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<input name="in" num_pins="6"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- Define LUT -->
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<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
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<input name="in" num_pins="6" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
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261e-12
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261e-12
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261e-12
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261e-12
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261e-12
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261e-12
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</delay_matrix>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
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<direct name="direct2" input="lut6.out" output="ff.D">
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<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
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<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
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</direct>
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<direct name="direct3" input="ble6.clk" output="ff.clk"/>
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<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
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<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
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</mux>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fle.in" output="ble6.in"/>
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<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
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<direct name="direct3" input="fle.clk" output="ble6.clk"/>
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</interconnect>
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</mode>
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<!-- 6-LUT mode definition end -->
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</pb_type>
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<interconnect>
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<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
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<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
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<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
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</complete>
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<complete name="clks" input="clb.clk" output="fle[9:0].clk">
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</complete>
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<direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
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</interconnect>
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<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
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<!-- Place this general purpose logic block in any unspecified column -->
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</pb_type>
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</complexblocklist>
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<?xml version="1.0" ?>
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<architecture>
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<models>
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<model name="io">
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<input_ports>
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<port name="outpad"/>
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</input_ports>
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<output_ports>
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<port name="inpad"/>
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</output_ports>
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</model>
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</models>
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<tiles>
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<tile name="io" area="0">
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<sub_tile name="io" capacity="8">
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<equivalent_sites>
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<site pb_type="io"/>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="custom">
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<loc side="left">io.outpad io.inpad</loc>
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<loc side="top">io.outpad io.inpad</loc>
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<loc side="right">io.outpad io.inpad</loc>
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<loc side="bottom">io.outpad io.inpad</loc>
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</pinlocations>
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</sub_tile>
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</tile>
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<tile name="clb" area="53894">
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<sub_tile name="clb">
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<equivalent_sites>
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<site pb_type="clb"/>
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</equivalent_sites>
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<input name="I" num_pins="40" equivalent="full"/>
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<output name="O" num_pins="20" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="spread"/>
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</sub_tile>
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</tile>
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</tiles>
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<!-- Physical descriptions begin -->
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<layout tileable="true">
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<auto_layout aspect_ratio="1.0">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</auto_layout>
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</layout>
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<device>
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<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
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<area grid_logic_tile_area="0"/>
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<chan_width_distr>
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<x distr="uniform" peak="1.000000"/>
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<switch_block type="wilton" fs="3"/>
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<connection_block input_switch_name="ipin_cblock"/>
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</device>
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<switchlist>
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<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
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<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
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</switchlist>
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<segmentlist>
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<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
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<mux name="0"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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</segment>
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</segmentlist>
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<complexblocklist>
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<pb_type name="io">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<mode name="physical" disable_packing="true">
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<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="iopad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
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</direct>
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<direct name="inpad" input="iopad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="inpad">
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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</direct>
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</interconnect>
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</mode>
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<power method="ignore"/>
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</pb_type>
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<pb_type name="clb">
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<input name="I" num_pins="40" equivalent="full"/>
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<output name="O" num_pins="20" equivalent="none"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="fle" num_pb="10">
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<input name="in" num_pins="6"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- physical mode -->
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<mode name="physical" disable_packing="true">
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<!-- Define 6-LUT mode -->
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<pb_type name="ble6" num_pb="1">
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<input name="in" num_pins="6"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- Define LUT -->
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<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
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<input name="in" num_pins="6" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
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261e-12
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261e-12
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261e-12
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261e-12
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261e-12
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261e-12
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</delay_matrix>
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</pb_type>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
|
||||
<direct name="direct2" input="lut6.out" output="ff.D">
|
||||
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
|
||||
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
|
||||
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- end of physical mode -->
|
||||
<!-- 6-LUT mode definition begin -->
|
||||
<mode name="n1_lut6">
|
||||
<!-- Define 6-LUT mode -->
|
||||
<pb_type name="ble6" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Define LUT -->
|
||||
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="6" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
|
||||
<direct name="direct2" input="lut6.out" output="ff.D">
|
||||
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
|
||||
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
|
||||
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- n1_lut6 -->
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
|
||||
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
|
||||
<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
|
||||
</complete>
|
||||
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
|
||||
</complete>
|
||||
<direct name="clbouts1" input="fle[9:0].out" output="clb.O[9:0]"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
</complexblocklist>
|
||||
</architecture>
|
||||
Loading…
Reference in New Issue