Fixed example
This commit is contained in:
Ganesh Gore
parent
b5e8434ca0
commit
1fca83f9c7
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@ -75,6 +75,9 @@ task.conf
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arch0=${PATH:TASK_DIR}/k6_N10_tileable_dpram8K_dsp36_40nm.xml
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arch1=${PATH:TASK_DIR}/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml
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.. code-block:: bash
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[BENCHMARKS]
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bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v
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bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v
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@ -85,6 +88,18 @@ task.conf
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OpenFPGA shell script
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~~~~~~~~~~~~~~~~~~~~~
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``*.openfpgashell`` script is simialr to TCL script for traditional FPGA CAD tools
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If you notice content of ``vtr_benchmark_template_script.openfpga`` file,
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it simply excutes the VPR tool. More commands are avaialble :ref:`_openfpga_commands`
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.. code-block:: bash
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# Execute VPR for architecture exploration
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} \
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--route_chan_width ${VPR_ROUTE_CHAN_WIDTH} \
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--constant_net_method route
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exit
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Architecture Files
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~~~~~~~~~~~~~~~~~~
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@ -107,4 +122,17 @@ Analyze Results
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.. code-block:: bash
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column -t -s, lab1/latest/task_result.csv | less -S
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column -t -s, lab1/latest/task_result.csv | less -S
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.. code-block:: csv
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name ,TotalRunTime , clb_blocks ,total_wire_length
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00_memset_ , 1 , 31 , 2217
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01_memset_ , 6 , 25 , 2120
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00_diffeq_paj_convert_ , 16 , 368 , 43526
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01_diffeq_paj_convert_ , 45 , 276 , 38465
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00_diffeq_f_systemC_ , 16 , 354 , 37245
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01_diffeq_f_systemC_ , 42 , 262 , 32722
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00_sha1_ , 9 , 168 , 16099
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01_sha1_ , 14 , 153 , 15274
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19
openfpga.sh
19
openfpga.sh
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@ -41,15 +41,15 @@ create-task () {
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return
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fi
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template="template_tasks/yosys_vpr_template"
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if [ ${#2} -ge 1 ]; then
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if [ ${#2} -ge 1 ]; then
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if [[ "$2" == "vpr_blif" ]]; then template="template_tasks/${2}_template/";
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elif [[ "$2" == "yosys_vpr" ]]; then template="template_tasks/${2}_template/";
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elif [[ "$2" == "vtr_benchmarks" ]]; then template="template_tasks/${2}_template/";
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else template="$2"
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elif [[ "$2" == "yosys_vpr" ]]; then template="template_tasks/${2}_template/";
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elif [[ "$2" == "vtr_benchmarks" ]]; then template="template_tasks/${2}_template/";
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else template="$2"
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fi
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fi
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if [ ! -f $OPENFPGA_PATH/openfpga_flow/tasks/${template}/config/task.conf ]; then
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echo "Template project [${template}] does not exist" ; return;
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if [ ! -f $OPENFPGA_PATH/openfpga_flow/tasks/${template}/config/task.conf ]; then
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echo "Template project [${template}] does not exist" ; return;
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fi
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echo "Creating task $1"
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echo "Template project ${template}"
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@ -57,6 +57,11 @@ create-task () {
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cp -r $OPENFPGA_PATH/openfpga_flow/tasks/${template}/* $1/
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}
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rerun-task () {
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$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" --remove_run_dir all
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$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@"
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}
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run-task () {
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$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@"
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}
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@ -66,7 +71,7 @@ clean-run () {
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}
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clear-task-run () {
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$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" --remove_run_dir all
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$PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" --remove_run_dir all
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}
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run-modelsim () {
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@ -398,8 +398,9 @@ def generate_each_task_actions(taskname):
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archfile=arch,
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benchmark_obj=bench,
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param=param,
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task_conf=task_conf,
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task_conf=task_conf
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)
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command += ["--flow_config", curr_task_conf_file]
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flow_run_cmd_list.append(
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{
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"arch": arch,
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@ -506,6 +507,7 @@ def create_run_command(curr_job_dir, archfile, benchmark_obj, param, task_conf):
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if args.debug:
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command += ["--debug"]
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return command
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@ -43,4 +43,8 @@ bench3_top = diffeq_f_systemC
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bench4_top = sha1
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[SCRIPT_PARAM_]
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#
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#
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[DEFAULT_PARSE_RESULT_VPR]
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01_lut6_use = "lut6 : ([0-9]+)", int
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02_lut5_use = "lut5 : ([0-9]+)", int
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@ -1,17 +1,6 @@
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<?xml version="1.0" ?>
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<architecture>
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<models>
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<model name="adder">
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<input_ports>
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<port name="a" combinational_sink_ports="sumout cout"/>
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<port name="b" combinational_sink_ports="sumout cout"/>
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<port name="cin" combinational_sink_ports="sumout cout"/>
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</input_ports>
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<output_ports>
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<port name="cout"/>
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<port name="sumout"/>
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</output_ports>
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</model>
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<model name="io">
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<input_ports>
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<port name="outpad"/>
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@ -20,16 +9,6 @@
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<port name="inpad"/>
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</output_ports>
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</model>
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<model name="frac_lut6">
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<input_ports>
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<port name="in"/>
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</input_ports>
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<output_ports>
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<port name="lut4_out"/>
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<port name="lut5_out"/>
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<port name="lut6_out"/>
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</output_ports>
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</model>
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</models>
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<tiles>
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<tile name="io" area="0">
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@ -160,87 +139,6 @@
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<output name="out" num_pins="2"/>
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<output name="cout" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- Physical mode definition begin (physical implementation of the fle) -->
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<mode name="physical" disable_packing="true">
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<pb_type name="fabric" num_pb="1">
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<input name="in" num_pins="6"/>
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<input name="cin" num_pins="1"/>
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<output name="out" num_pins="2"/>
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<output name="cout" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="frac_logic" num_pb="1">
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<input name="in" num_pins="6"/>
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<output name="lut4_out" num_pins="4"/>
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<output name="out" num_pins="2"/>
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<!-- Define LUT -->
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<pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
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<input name="in" num_pins="6"/>
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<output name="lut4_out" num_pins="4"/>
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<output name="lut5_out" num_pins="2"/>
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<output name="lut6_out" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
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<direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
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<direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
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<mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
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</interconnect>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<!-- Define adders -->
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<pb_type name="adder" blif_model=".subckt adder" num_pb="2">
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<input name="a" num_pins="1"/>
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<input name="b" num_pins="1"/>
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<input name="cin" num_pins="1"/>
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<output name="cout" num_pins="1"/>
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<output name="sumout" num_pins="1"/>
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<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
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<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
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<delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
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<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
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<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
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<delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
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<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
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<direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
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<direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
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<direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
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<direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
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<direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
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<direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
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<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
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<complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
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<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
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<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
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</mux>
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<mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
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<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
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</mux>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fle.in" output="fabric.in"/>
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<direct name="direct2" input="fle.cin" output="fabric.cin"/>
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<direct name="direct3" input="fabric.out" output="fle.out"/>
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<direct name="direct4" input="fabric.cout" output="fle.cout"/>
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<direct name="direct5" input="fle.clk" output="fabric.clk"/>
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</interconnect>
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</mode>
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<!-- Physical mode definition end (physical implementation of the fle) -->
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<!-- n2_lut5 -->
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<mode name="n1_lut6">
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<pb_type name="ble6" num_pb="1">
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<input name="in" num_pins="6"/>
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@ -290,12 +188,10 @@
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<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
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<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
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</complete>
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<complete name="clks" input="clb.clk" output="fle[9:0].clk">
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</complete>
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<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
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<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
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</interconnect>
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</pb_type>
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</complexblocklist>
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@ -1,17 +1,6 @@
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<?xml version="1.0" ?>
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<architecture>
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<models>
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<model name="adder">
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<input_ports>
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<port name="a" combinational_sink_ports="sumout cout"/>
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<port name="b" combinational_sink_ports="sumout cout"/>
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<port name="cin" combinational_sink_ports="sumout cout"/>
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</input_ports>
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<output_ports>
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<port name="cout"/>
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<port name="sumout"/>
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</output_ports>
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</model>
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<model name="io">
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<input_ports>
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<port name="outpad"/>
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@ -20,16 +9,6 @@
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<port name="inpad"/>
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</output_ports>
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</model>
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<model name="frac_lut6">
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<input_ports>
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<port name="in"/>
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</input_ports>
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<output_ports>
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<port name="lut4_out"/>
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<port name="lut5_out"/>
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<port name="lut6_out"/>
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</output_ports>
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</model>
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</models>
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<tiles>
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<tile name="io" area="0">
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@ -160,140 +139,7 @@
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<output name="out" num_pins="2"/>
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<output name="cout" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- Physical mode definition begin (physical implementation of the fle) -->
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<mode name="physical" disable_packing="true">
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<pb_type name="fabric" num_pb="1">
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<input name="in" num_pins="6"/>
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<input name="cin" num_pins="1"/>
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<output name="out" num_pins="2"/>
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<output name="cout" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="frac_logic" num_pb="1">
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<input name="in" num_pins="6"/>
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<output name="lut4_out" num_pins="4"/>
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<output name="out" num_pins="2"/>
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<!-- Define LUT -->
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<pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
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<input name="in" num_pins="6"/>
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<output name="lut4_out" num_pins="4"/>
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<output name="lut5_out" num_pins="2"/>
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<output name="lut6_out" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
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<direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
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<direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
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<mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
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</interconnect>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="66e-12" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
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</pb_type>
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<!-- Define adders -->
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<pb_type name="adder" blif_model=".subckt adder" num_pb="2">
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<input name="a" num_pins="1"/>
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<input name="b" num_pins="1"/>
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<input name="cin" num_pins="1"/>
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<output name="cout" num_pins="1"/>
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<output name="sumout" num_pins="1"/>
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<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
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<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
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<delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
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<delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
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<delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
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<delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
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<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
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<direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
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<direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
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<direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
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<direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
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<direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
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<direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
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<direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
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<complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
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<mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
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<!-- LUT to output is faster than FF to output on a Stratix IV -->
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<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
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<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
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</mux>
|
||||
<mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="fabric.in"/>
|
||||
<direct name="direct2" input="fle.cin" output="fabric.cin"/>
|
||||
<direct name="direct3" input="fabric.out" output="fle.out"/>
|
||||
<direct name="direct4" input="fabric.cout" output="fle.cout"/>
|
||||
<direct name="direct5" input="fle.clk" output="fabric.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Physical mode definition end (physical implementation of the fle) -->
|
||||
<!-- BEGIN fle mode of dual lut5 -->
|
||||
<mode name="n2_lut5">
|
||||
<pb_type name="ble5" num_pb="2">
|
||||
<input name="in" num_pins="5"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Regular LUT mode -->
|
||||
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="5" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||
we instead take the average of these numbers to get more stable results
|
||||
82e-12
|
||||
173e-12
|
||||
261e-12
|
||||
263e-12
|
||||
398e-12
|
||||
-->
|
||||
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
|
||||
235e-12
|
||||
235e-12
|
||||
235e-12
|
||||
235e-12
|
||||
235e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble5.in" output="lut5.in"/>
|
||||
<direct name="direct2" input="lut5.out" output="ff.D">
|
||||
<pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble5.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
|
||||
<delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
|
||||
<direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
|
||||
<complete name="direct3" input="fle.clk" output="ble5.clk"/>
|
||||
<direct name="direct4" input="ble5.out" output="fle.out"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- n2_lut5 -->
|
||||
<!-- start n1_lut6 -->
|
||||
<mode name="n1_lut6">
|
||||
<pb_type name="ble6" num_pb="1">
|
||||
<input name="in" num_pins="6"/>
|
||||
|
|
@ -331,24 +177,68 @@
|
|||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
|
||||
<direct name="direct1" input="fle.in" output="ble6.in"/>
|
||||
<direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- n1_lut6 -->
|
||||
<!-- end n1_lut6 -->
|
||||
<!-- start n1_lut5 -->
|
||||
<mode name="n1_lut5">
|
||||
<pb_type name="ble5" num_pb="2">
|
||||
<input name="in" num_pins="5"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="5" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble5.in" output="lut5[0:0].in"/>
|
||||
<direct name="direct2" input="lut5.out" output="ff.D">
|
||||
<pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble5.clk" output="ff.clk"/>
|
||||
<mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
|
||||
<delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
|
||||
<direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
|
||||
<direct name="direct3" input="ble5[0:0].out" output="fle.out[0:0]"/>
|
||||
<direct name="direct4" input="ble5[1:1].out" output="fle.out[1:1]"/>
|
||||
<direct name="direct5" input="fle.clk" output="ble5[0:0].clk"/>
|
||||
<direct name="direct6" input="fle.clk" output="ble5[1:1].clk"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- end n1_lut5 -->
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
|
||||
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
|
||||
<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
|
||||
</complete>
|
||||
|
||||
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
|
||||
</complete>
|
||||
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
|
||||
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
|
||||
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
</complexblocklist>
|
||||
|
|
|
|||
Loading…
Reference in New Issue