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[core] fixed the bug which causes wrong fpga top connections and failed in fpga sdc

This commit is contained in:
tangxifan 2023-06-19 11:59:48 -07:00
parent 63ee0c980e
commit a4f26798b0
4 changed files with 31 additions and 14 deletions
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2
openfpga/src/fabric/build_device_module.cpp
View File

@ -154,7 +154,7 @@ int add_fpga_core_to_device_module_graph(ModuleManager& module_manager,
/* Create a wrapper module under the existing fpga_top */
ModuleId new_top_module = module_manager.create_wrapper_module(
top_module, top_module_name, core_inst_name, frame_view);
top_module, top_module_name, core_inst_name, !frame_view);
if (!module_manager.valid_module_id(new_top_module)) {
VTR_LOGV_ERROR(verbose,
"Failed to create a wrapper module '%s' on top of '%s'!\n",

25
openfpga/src/fabric/module_manager.cpp
View File

@ -1257,9 +1257,6 @@ ModuleId ModuleManager::create_wrapper_module(
reserve_module_nets(wrapper_module, num_nets_to_reserve);
for (ModulePortId new_port : module_ports(wrapper_module)) {
BasicPort new_port_info = module_port(wrapper_module, new_port);
/* Create new net */
ModuleNetId new_net = create_module_net(wrapper_module);
VTR_ASSERT(valid_module_net_id(wrapper_module, new_net));
/* For each input pin, create a new source */
ModuleManager::e_module_port_type new_port_type =
port_type(wrapper_module, new_port);
@ -1267,26 +1264,28 @@ ModuleId ModuleManager::create_wrapper_module(
ModulePortId existing_port = port_map[new_port];
BasicPort existing_port_info = module_port(existing_module, existing_port);
VTR_ASSERT(existing_port_info == new_port_info);
reserve_module_net_sources(wrapper_module, new_net,
new_port_info.pins().size());
reserve_module_net_sinks(wrapper_module, new_net,
new_port_info.pins().size());
if (new_port_type !=
ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT) {
for (auto pin : new_port_info.pins()) {
for (size_t ipin = 0; ipin < new_port_info.pins().size(); ++ipin) {
/* Create new net */
ModuleNetId new_net = create_module_net(wrapper_module);
VTR_ASSERT(valid_module_net_id(wrapper_module, new_net));
add_module_net_source(wrapper_module, new_net, wrapper_module, 0,
new_port, pin);
new_port, new_port_info.pins()[ipin]);
add_module_net_sink(wrapper_module, new_net, existing_module, 0,
existing_port, pin);
existing_port, existing_port_info.pins()[ipin]);
}
} else {
VTR_ASSERT_SAFE(new_port_type ==
ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT);
for (auto pin : new_port_info.pins()) {
for (size_t ipin = 0; ipin < new_port_info.pins().size(); ++ipin) {
/* Create new net */
ModuleNetId new_net = create_module_net(wrapper_module);
VTR_ASSERT(valid_module_net_id(wrapper_module, new_net));
add_module_net_source(wrapper_module, new_net, existing_module, 0,
existing_port, pin);
existing_port, new_port_info.pins()[ipin]);
add_module_net_sink(wrapper_module, new_net, wrapper_module, 0,
new_port, pin);
new_port, existing_port_info.pins()[ipin]);
}
}
}

9
openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
View File

@ -258,6 +258,15 @@ void print_analysis_sdc(const AnalysisSdcOption& option,
ModuleId top_module =
openfpga_ctx.module_graph().find_module(generate_fpga_top_module_name());
VTR_ASSERT(true == openfpga_ctx.module_graph().valid_module_id(top_module));
/* Use the core module as the top when the fpga_core is added */
std::string core_block_name = generate_fpga_core_module_name();
const ModuleId& core_module =
openfpga_ctx.module_graph().find_module(core_block_name);
if (openfpga_ctx.module_graph().valid_module_id(core_module)) {
/* Now we use the core_block as the top-level block for the remaining
* functions */
top_module = core_module;
}
/* Create clock and set I/O ports with input/output delays
* FIXME: Now different I/Os have different delays due to multiple clock

9
openfpga/src/fpga_sdc/pnr_sdc_writer.cpp
View File

@ -351,6 +351,15 @@ void print_pnr_sdc(const PnrSdcOption& sdc_options,
ModuleId top_module = module_manager.find_module(top_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(top_module));
/* Use the core module as the top when the fpga_core is added */
std::string core_block_name = generate_fpga_core_module_name();
const ModuleId& core_module = module_manager.find_module(core_block_name);
if (module_manager.valid_module_id(core_module)) {
/* Now we use the core_block as the top-level block for the remaining
* functions */
top_module = core_module;
}
/* Constrain global ports */
if (true == sdc_options.constrain_global_port()) {
print_pnr_sdc_global_ports(sdc_options, module_manager, top_module,