177 lines
7.2 KiB
C++
177 lines
7.2 KiB
C++
/********************************************************************
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* This file includes the main function to build module graphs
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* for the FPGA fabric
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "vtr_time.h"
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/* Headers from openfpgashell library */
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#include "build_decoder_modules.h"
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#include "build_device_module.h"
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#include "build_essential_modules.h"
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#include "build_grid_modules.h"
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#include "build_lut_modules.h"
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#include "build_memory_modules.h"
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#include "build_mux_modules.h"
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#include "build_routing_modules.h"
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#include "build_top_module.h"
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#include "build_wire_modules.h"
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#include "command_exit_codes.h"
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#include "openfpga_naming.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* The main function to be called for building module graphs
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* for a FPGA fabric
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*******************************************************************/
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int build_device_module_graph(
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ModuleManager& module_manager, DecoderLibrary& decoder_lib,
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MemoryBankShiftRegisterBanks& blwl_sr_banks,
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const OpenfpgaContext& openfpga_ctx, const DeviceContext& vpr_device_ctx,
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const bool& frame_view, const bool& compress_routing,
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const bool& duplicate_grid_pin, const FabricKey& fabric_key,
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const bool& generate_random_fabric_key, const bool& verbose) {
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vtr::ScopedStartFinishTimer timer("Build fabric module graph");
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int status = CMD_EXEC_SUCCESS;
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CircuitModelId sram_model =
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openfpga_ctx.arch().config_protocol.memory_model();
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VTR_ASSERT(true ==
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openfpga_ctx.arch().circuit_lib.valid_model_id(sram_model));
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/* Add constant generator modules: VDD and GND */
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build_constant_generator_modules(module_manager);
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/* Register all the user-defined modules in the module manager
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* This should be done prior to other steps in this function,
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* because they will be instanciated by other primitive modules
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*/
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build_user_defined_modules(module_manager, openfpga_ctx.arch().circuit_lib);
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/* Build elmentary modules */
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build_essential_modules(module_manager, openfpga_ctx.arch().circuit_lib);
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/* Build local encoders for multiplexers, this MUST be called before
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* multiplexer building */
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build_mux_local_decoder_modules(module_manager, openfpga_ctx.mux_lib(),
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openfpga_ctx.arch().circuit_lib);
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/* Build multiplexer modules */
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build_mux_modules(module_manager, openfpga_ctx.mux_lib(),
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openfpga_ctx.arch().circuit_lib);
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/* Build LUT modules */
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build_lut_modules(module_manager, openfpga_ctx.arch().circuit_lib);
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/* Build wire modules */
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build_wire_modules(module_manager, openfpga_ctx.arch().circuit_lib);
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/* Build memory modules */
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build_memory_modules(module_manager, decoder_lib, openfpga_ctx.mux_lib(),
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openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.arch().config_protocol.type());
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/* Build grid and programmable block modules */
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build_grid_modules(module_manager, decoder_lib, vpr_device_ctx,
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openfpga_ctx.vpr_device_annotation(),
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openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(),
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openfpga_ctx.arch().config_protocol.type(), sram_model,
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duplicate_grid_pin, verbose);
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if (true == compress_routing) {
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build_unique_routing_modules(
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module_manager, decoder_lib, vpr_device_ctx,
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openfpga_ctx.vpr_device_annotation(), openfpga_ctx.device_rr_gsb(),
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openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.arch().config_protocol.type(), sram_model, verbose);
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} else {
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VTR_ASSERT_SAFE(false == compress_routing);
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build_flatten_routing_modules(
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module_manager, decoder_lib, vpr_device_ctx,
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openfpga_ctx.vpr_device_annotation(), openfpga_ctx.device_rr_gsb(),
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openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.arch().config_protocol.type(), sram_model, verbose);
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}
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/* Build FPGA fabric top-level module */
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status = build_top_module(
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module_manager, decoder_lib, blwl_sr_banks, openfpga_ctx.arch().circuit_lib,
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openfpga_ctx.clock_arch(), openfpga_ctx.clock_rr_lookup(),
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openfpga_ctx.vpr_device_annotation(), vpr_device_ctx.grid,
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openfpga_ctx.arch().tile_annotations, vpr_device_ctx.rr_graph,
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openfpga_ctx.device_rr_gsb(), openfpga_ctx.tile_direct(),
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openfpga_ctx.arch().arch_direct, openfpga_ctx.arch().config_protocol,
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sram_model, frame_view, compress_routing, duplicate_grid_pin, fabric_key,
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generate_random_fabric_key);
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if (CMD_EXEC_FATAL_ERROR == status) {
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return status;
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}
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/* Now a critical correction has to be done!
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* In the module construction, we always use prefix of ports because they are
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* binded to the ports in architecture description (logic blocks etc.) To
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* interface with standard cell, we should rename the ports of primitive
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* modules using lib_name instead of prefix (which have no children and are
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* probably linked to a standard cell!)
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*/
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rename_primitive_module_port_names(module_manager,
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openfpga_ctx.arch().circuit_lib);
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return status;
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}
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/********************************************************************
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* The main function to be called for adding the fpga_core wrapper to a FPGA
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*fabric
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* - Rename existing fpga_top to fpga_core
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* - Create a wrapper module 'fpga_top' on the fpga_core
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*******************************************************************/
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int add_fpga_core_to_device_module_graph(ModuleManager& module_manager,
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const std::string& core_inst_name,
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const bool& frame_view,
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const bool& verbose) {
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int status = CMD_EXEC_SUCCESS;
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/* Execute the module graph api */
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std::string top_module_name = generate_fpga_top_module_name();
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ModuleId top_module = module_manager.find_module(top_module_name);
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if (!module_manager.valid_module_id(top_module)) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* Rename existing top module to fpga_core */
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std::string core_module_name = generate_fpga_core_module_name();
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module_manager.set_module_name(top_module, core_module_name);
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VTR_LOGV(verbose, "Rename current top-level module '%s' to '%s'\n",
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top_module_name.c_str(), core_module_name.c_str());
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/* Create a wrapper module under the existing fpga_top */
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ModuleId new_top_module = module_manager.create_wrapper_module(
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top_module, top_module_name, core_inst_name, !frame_view);
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if (!module_manager.valid_module_id(new_top_module)) {
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VTR_LOGV_ERROR(verbose,
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"Failed to create a wrapper module '%s' on top of '%s'!\n",
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top_module_name.c_str(), core_module_name.c_str());
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return CMD_EXEC_FATAL_ERROR;
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}
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VTR_LOGV(verbose, "Created a wrapper module '%s' on top of '%s'\n",
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top_module_name.c_str(), core_module_name.c_str());
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/* Now fpga_core should be the only configurable child under the top-level
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* module */
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module_manager.add_configurable_child(new_top_module, top_module, 0);
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/* TODO: Update the fabric global ports */
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return status;
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}
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} /* end namespace openfpga */
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