Merge pull request #349 from lnis-uofu/testbench_flag

More micro benchmarks on adder

openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v

@@ -0,0 +1,21 @@
+// Creating a scaleable adder
+
+module adder_16(cout, sum, a, b, cin);
+parameter size = 6;  /* declare a parameter. default required */
+output cout;
+output [size-1:0] sum; 	 // sum uses the size parameter
+input cin;
+input [size-1:0] a, b;  // 'a' and 'b' use the size parameter
+
+assign {cout, sum} = a + b + cin;
+
+endmodule
+
+
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+

openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v

@@ -0,0 +1,21 @@
+// Creating a scaleable adder
+
+module adder_4(cout, sum, a, b, cin);
+parameter size = 4;  /* declare a parameter. default required */
+output cout;
+output [size-1:0] sum; 	 // sum uses the size parameter
+input cin;
+input [size-1:0] a, b;  // 'a' and 'b' use the size parameter
+
+assign {cout, sum} = a + b + cin;
+
+endmodule
+
+
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+

openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v

@@ -0,0 +1,21 @@
+// Creating a scaleable adder
+
+module adder_6(cout, sum, a, b, cin);
+parameter size = 6;  /* declare a parameter. default required */
+output cout;
+output [size-1:0] sum; 	 // sum uses the size parameter
+input cin;
+input [size-1:0] a, b;  // 'a' and 'b' use the size parameter
+
+assign {cout, sum} = a + b + cin;
+
+endmodule
+
+
+
+
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+

openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf

@@ -27,18 +27,20 @@ yosys_args = -family qlf_k4n8 -no_ff_map
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
 
 [BENCHMARKS]
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v
+bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
 
 [SYNTHESIS_PARAM]
 bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
 bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
 
-bench1_top = adder_8
+bench0_top = adder_4
+bench1_top = adder_6
+bench2_top = adder_8
+bench3_top = adder_16
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-##########################
-# The output verilog of yosys is not synthesizable!!!
-# Turn off verification for now
-# SHOULD focus on fixing the Verilog problem and run verification at the end of the flow
 end_flow_with_test=
 vpr_fpga_verilog_formal_verification_top_netlist=