From 4d4577bb835779a90578d65b902ac1aa9f058d6a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 30 Jun 2021 15:13:47 -0600
Subject: [PATCH 1/3] [Benchmark] Added multiple adder benchmarks to have
 better coverage in testing FPGA arch with adders

---
 .../micro_benchmark/adder/adder_16/adder_16.v | 21 ++++++
 .../micro_benchmark/adder/adder_4/adder_4.v   | 21 ++++++
 .../micro_benchmark/adder/adder_6/adder_6.v   | 21 ++++++
 .../{ => adder}/adder_8/adder_8.act           |  0
 .../{ => adder}/adder_8/adder_8.eblif         |  0
 .../{ => adder}/adder_8/adder_8.v             |  0
 .../{ => adder}/adder_8/adder_8_out.v         |  0
 .../adder/adder_8/adder_8_post_synthesis.v    | 65 +++++++++++++++++++
 8 files changed, 128 insertions(+)
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v
 rename openfpga_flow/benchmarks/micro_benchmark/{ => adder}/adder_8/adder_8.act (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/{ => adder}/adder_8/adder_8.eblif (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/{ => adder}/adder_8/adder_8.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/{ => adder}/adder_8/adder_8_out.v (100%)
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v

diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
new file mode 100644
index 000000000..2e7d31076
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
@@ -0,0 +1,21 @@
+// Creating a scaleable adder
+
+module adder_16(cout, sum, a, b, cin);
+parameter size = 6;  /* declare a parameter. default required */
+output cout;
+output [size-1:0] sum; 	 // sum uses the size parameter
+input cin;
+input [size-1:0] a, b;  // 'a' and 'b' use the size parameter
+
+assign {cout, sum} = a + b + cin;
+
+endmodule
+
+
+
+
+
+
+
+
+
diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v
new file mode 100644
index 000000000..b444bfa3a
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v
@@ -0,0 +1,21 @@
+// Creating a scaleable adder
+
+module adder_4(cout, sum, a, b, cin);
+parameter size = 4;  /* declare a parameter. default required */
+output cout;
+output [size-1:0] sum; 	 // sum uses the size parameter
+input cin;
+input [size-1:0] a, b;  // 'a' and 'b' use the size parameter
+
+assign {cout, sum} = a + b + cin;
+
+endmodule
+
+
+
+
+
+
+
+
+
diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v
new file mode 100644
index 000000000..74a09005d
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v
@@ -0,0 +1,21 @@
+// Creating a scaleable adder
+
+module adder_6(cout, sum, a, b, cin);
+parameter size = 6;  /* declare a parameter. default required */
+output cout;
+output [size-1:0] sum; 	 // sum uses the size parameter
+input cin;
+input [size-1:0] a, b;  // 'a' and 'b' use the size parameter
+
+assign {cout, sum} = a + b + cin;
+
+endmodule
+
+
+
+
+
+
+
+
+
diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.act
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.act
rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.act
diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.eblif
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.eblif
rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.eblif
diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v
rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_out.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8_out.v
rename to openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_out.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v
new file mode 100644
index 000000000..1e7069e8c
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v
@@ -0,0 +1,65 @@
+/* Generated by Yosys 0.9+2406 (git sha1 3a9968de, gcc 8.4.0 -fPIC -Os) */
+
+module adder_8(\a[0] , \a[1] , \a[2] , \a[3] , \a[4] , \a[5] , \a[6] , \a[7] , \b[0] , \b[1] , \b[2] , \b[3] , \b[4] , \b[5] , \b[6] , \b[7] , cin, cout, \sum[0] , \sum[1] , \sum[2] , \sum[3] , \sum[4] , \sum[5] , \sum[6] , \sum[7] );
+  wire _00_;
+  wire _01_;
+  wire _02_;
+  wire _03_;
+  wire _04_;
+  wire _05_;
+  wire _06_;
+  wire _07_;
+  wire _08_;
+  wire _09_;
+  wire _10_;
+  wire _11_;
+  wire _12_;
+  input \a[0] ;
+  input \a[1] ;
+  input \a[2] ;
+  input \a[3] ;
+  input \a[4] ;
+  input \a[5] ;
+  input \a[6] ;
+  input \a[7] ;
+  input \b[0] ;
+  input \b[1] ;
+  input \b[2] ;
+  input \b[3] ;
+  input \b[4] ;
+  input \b[5] ;
+  input \b[6] ;
+  input \b[7] ;
+  input cin;
+  output cout;
+  output \sum[0] ;
+  output \sum[1] ;
+  output \sum[2] ;
+  output \sum[3] ;
+  output \sum[4] ;
+  output \sum[5] ;
+  output \sum[6] ;
+  output \sum[7] ;
+  assign cout = 8'h8e >> { _00_, \a[7] , \b[7]  };
+  assign _08_ = 4'h8 >> { \a[5] , \b[5]  };
+  assign \sum[0]  = 8'h96 >> { \a[0] , \b[0] , cin };
+  assign \sum[1]  = 8'h69 >> { _05_, \a[1] , \b[1]  };
+  assign \sum[2]  = 16'h6a56 >> { _05_, \a[1] , \b[1] , _04_ };
+  assign \sum[3]  = 16'h9996 >> { _03_, _06_, \a[3] , \b[3]  };
+  assign \sum[4]  = 8'h69 >> { _02_, \a[4] , \b[4]  };
+  assign \sum[5]  = 8'h69 >> { _09_, \a[5] , \b[5]  };
+  assign _09_ = 8'h71 >> { _02_, \a[4] , \b[4]  };
+  assign \sum[6]  = 16'h9996 >> { _01_, _08_, \a[6] , \b[6]  };
+  assign \sum[7]  = 8'h69 >> { _00_, \a[7] , \b[7]  };
+  assign _00_ = 16'h011f >> { \a[6] , \b[6] , _01_, _08_ };
+  assign _01_ = 16'h4054 >> { _02_, \a[4] , \b[4] , _07_ };
+  assign _02_ = 16'h011f >> { \a[3] , \b[3] , _03_, _06_ };
+  assign _03_ = 16'h80a8 >> { _05_, \a[1] , \b[1] , _04_ };
+  assign _04_ = 4'h6 >> { \a[2] , \b[2]  };
+  assign _05_ = 8'h17 >> { \a[0] , \b[0] , cin };
+  assign _06_ = 4'h8 >> { \a[2] , \b[2]  };
+  assign _07_ = 4'h1 >> { \a[5] , \b[5]  };
+  assign _10_ = 1'h0;
+  assign _11_ = 1'h1;
+  assign _12_ = 1'hx;
+endmodule

From 83d177b13b11a9a2d77a00612f570667bdcdb38c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 30 Jun 2021 15:14:24 -0600
Subject: [PATCH 2/3] [Test] Deploy the newly added adder benchmarks to tests

---
 .../lut_adder_test/config/task.conf                | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
index 4f501a1c3..12f1bebe1 100644
--- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
+++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
@@ -27,18 +27,20 @@ yosys_args = -family qlf_k4n8 -no_ff_map
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
 
 [BENCHMARKS]
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_4/adder_4.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_6/adder_6.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8.v
+bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
 
 [SYNTHESIS_PARAM]
 bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
 bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
 
-bench1_top = adder_8
+bench0_top = adder_4
+bench1_top = adder_6
+bench2_top = adder_8
+bench3_top = adder_16
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-##########################
-# The output verilog of yosys is not synthesizable!!!
-# Turn off verification for now
-# SHOULD focus on fixing the Verilog problem and run verification at the end of the flow
 end_flow_with_test=
 vpr_fpga_verilog_formal_verification_top_netlist=

From a89853747404ea63eb9378763771d9d295069a4b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 30 Jun 2021 15:29:13 -0600
Subject: [PATCH 3/3] [Benchmark] Remove redundant post-synthesis netlist for
 ``adder_8``

---
 .../adder/adder_8/adder_8_post_synthesis.v    | 65 -------------------
 1 file changed, 65 deletions(-)
 delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v

diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v
deleted file mode 100644
index 1e7069e8c..000000000
--- a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_8/adder_8_post_synthesis.v
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Generated by Yosys 0.9+2406 (git sha1 3a9968de, gcc 8.4.0 -fPIC -Os) */
-
-module adder_8(\a[0] , \a[1] , \a[2] , \a[3] , \a[4] , \a[5] , \a[6] , \a[7] , \b[0] , \b[1] , \b[2] , \b[3] , \b[4] , \b[5] , \b[6] , \b[7] , cin, cout, \sum[0] , \sum[1] , \sum[2] , \sum[3] , \sum[4] , \sum[5] , \sum[6] , \sum[7] );
-  wire _00_;
-  wire _01_;
-  wire _02_;
-  wire _03_;
-  wire _04_;
-  wire _05_;
-  wire _06_;
-  wire _07_;
-  wire _08_;
-  wire _09_;
-  wire _10_;
-  wire _11_;
-  wire _12_;
-  input \a[0] ;
-  input \a[1] ;
-  input \a[2] ;
-  input \a[3] ;
-  input \a[4] ;
-  input \a[5] ;
-  input \a[6] ;
-  input \a[7] ;
-  input \b[0] ;
-  input \b[1] ;
-  input \b[2] ;
-  input \b[3] ;
-  input \b[4] ;
-  input \b[5] ;
-  input \b[6] ;
-  input \b[7] ;
-  input cin;
-  output cout;
-  output \sum[0] ;
-  output \sum[1] ;
-  output \sum[2] ;
-  output \sum[3] ;
-  output \sum[4] ;
-  output \sum[5] ;
-  output \sum[6] ;
-  output \sum[7] ;
-  assign cout = 8'h8e >> { _00_, \a[7] , \b[7]  };
-  assign _08_ = 4'h8 >> { \a[5] , \b[5]  };
-  assign \sum[0]  = 8'h96 >> { \a[0] , \b[0] , cin };
-  assign \sum[1]  = 8'h69 >> { _05_, \a[1] , \b[1]  };
-  assign \sum[2]  = 16'h6a56 >> { _05_, \a[1] , \b[1] , _04_ };
-  assign \sum[3]  = 16'h9996 >> { _03_, _06_, \a[3] , \b[3]  };
-  assign \sum[4]  = 8'h69 >> { _02_, \a[4] , \b[4]  };
-  assign \sum[5]  = 8'h69 >> { _09_, \a[5] , \b[5]  };
-  assign _09_ = 8'h71 >> { _02_, \a[4] , \b[4]  };
-  assign \sum[6]  = 16'h9996 >> { _01_, _08_, \a[6] , \b[6]  };
-  assign \sum[7]  = 8'h69 >> { _00_, \a[7] , \b[7]  };
-  assign _00_ = 16'h011f >> { \a[6] , \b[6] , _01_, _08_ };
-  assign _01_ = 16'h4054 >> { _02_, \a[4] , \b[4] , _07_ };
-  assign _02_ = 16'h011f >> { \a[3] , \b[3] , _03_, _06_ };
-  assign _03_ = 16'h80a8 >> { _05_, \a[1] , \b[1] , _04_ };
-  assign _04_ = 4'h6 >> { \a[2] , \b[2]  };
-  assign _05_ = 8'h17 >> { \a[0] , \b[0] , cin };
-  assign _06_ = 4'h8 >> { \a[2] , \b[2]  };
-  assign _07_ = 4'h1 >> { \a[5] , \b[5]  };
-  assign _10_ = 1'h0;
-  assign _11_ = 1'h1;
-  assign _12_ = 1'hx;
-endmodule