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[FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks

This commit is contained in:
tangxifan 2021-10-01 16:23:38 -07:00
parent 4f7ab01bf5
commit 9e5debabe1
5 changed files with 15 additions and 6 deletions
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8
openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp
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@ -190,11 +190,12 @@ int write_memory_bank_fabric_bitstream_to_text_file(std::fstream& fp,
*******************************************************************/ *******************************************************************/
static static
int write_memory_bank_flatten_fabric_bitstream_to_text_file(std::fstream& fp, int write_memory_bank_flatten_fabric_bitstream_to_text_file(std::fstream& fp,
const bool& fast_configuration,
const bool& bit_value_to_skip, const bool& bit_value_to_skip,
const FabricBitstream& fabric_bitstream) { const FabricBitstream& fabric_bitstream) {
int status = 0; int status = 0;
MemoryBankFlattenFabricBitstream fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, bit_value_to_skip); MemoryBankFlattenFabricBitstream fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip);
/* The address sizes and data input sizes are the same across any element, /* The address sizes and data input sizes are the same across any element,
* just get it from the 1st element to save runtime * just get it from the 1st element to save runtime
@ -234,11 +235,12 @@ int write_memory_bank_flatten_fabric_bitstream_to_text_file(std::fstream& fp,
*******************************************************************/ *******************************************************************/
static static
int write_memory_bank_shift_register_fabric_bitstream_to_text_file(std::fstream& fp, int write_memory_bank_shift_register_fabric_bitstream_to_text_file(std::fstream& fp,
const bool& fast_configuration,
const bool& bit_value_to_skip, const bool& bit_value_to_skip,
const FabricBitstream& fabric_bitstream) { const FabricBitstream& fabric_bitstream) {
int status = 0; int status = 0;
MemoryBankShiftRegisterFabricBitstream fabric_bits = build_memory_bank_shift_register_fabric_bitstream(fabric_bitstream, bit_value_to_skip); MemoryBankShiftRegisterFabricBitstream fabric_bits = build_memory_bank_shift_register_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip);
/* Output information about how to intepret the bitstream */ /* Output information about how to intepret the bitstream */
fp << "// Bitstream word count: " << fabric_bits.num_words() << std::endl; fp << "// Bitstream word count: " << fabric_bits.num_words() << std::endl;
@ -415,11 +417,13 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage
fabric_bitstream); fabric_bitstream);
} else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) { } else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) {
status = write_memory_bank_flatten_fabric_bitstream_to_text_file(fp, status = write_memory_bank_flatten_fabric_bitstream_to_text_file(fp,
apply_fast_configuration,
bit_value_to_skip, bit_value_to_skip,
fabric_bitstream); fabric_bitstream);
} else { } else {
VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type()); VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type());
status = write_memory_bank_shift_register_fabric_bitstream_to_text_file(fp, status = write_memory_bank_shift_register_fabric_bitstream_to_text_file(fp,
apply_fast_configuration,
bit_value_to_skip, bit_value_to_skip,
fabric_bitstream); fabric_bitstream);
} }

2
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -862,7 +862,7 @@ size_t calculate_num_config_clock_cycles(const ConfigProtocol& config_protocol,
100. * ((float)num_config_clock_cycles / (float)full_num_config_clock_cycles - 1.)); 100. * ((float)num_config_clock_cycles / (float)full_num_config_clock_cycles - 1.));
} }
} else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) { } else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) {
num_config_clock_cycles = 1 + build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, bit_value_to_skip).size(); num_config_clock_cycles = 1 + build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip).size();
} else if (BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type()) { } else if (BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type()) {
/* TODO */ /* TODO */
} }

1
openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
View File

@ -187,6 +187,7 @@ void print_verilog_full_testbench_ql_memory_bank_flatten_bitstream(std::fstream&
/* Reorganize the fabric bitstream by the same address across regions */ /* Reorganize the fabric bitstream by the same address across regions */
MemoryBankFlattenFabricBitstream fabric_bits_by_addr = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, MemoryBankFlattenFabricBitstream fabric_bits_by_addr = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream,
fast_configuration,
bit_value_to_skip); bit_value_to_skip);
/* Feed address and data input pair one by one /* Feed address and data input pair one by one

8
openfpga/src/utils/fabric_bitstream_utils.cpp
View File

@ -233,14 +233,15 @@ MemoryBankFabricBitstream build_memory_bank_fabric_bitstream_by_address(const Fa
} }
MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(const FabricBitstream& fabric_bitstream, MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(const FabricBitstream& fabric_bitstream,
const bool& fast_configuration,
const bool& bit_value_to_skip) { const bool& bit_value_to_skip) {
/* Build the bitstream by each region, here we use (WL, BL) pairs when storing bitstreams */ /* Build the bitstream by each region, here we use (WL, BL) pairs when storing bitstreams */
vtr::vector<FabricBitRegionId, std::map<std::string, std::string>> fabric_bits_per_region; vtr::vector<FabricBitRegionId, std::map<std::string, std::string>> fabric_bits_per_region;
fabric_bits_per_region.resize(fabric_bitstream.num_regions()); fabric_bits_per_region.resize(fabric_bitstream.num_regions());
for (const FabricBitRegionId& region : fabric_bitstream.regions()) { for (const FabricBitRegionId& region : fabric_bitstream.regions()) {
for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) { for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) {
/* Skip din because they should be pre-configured through programming reset/set */ /* Only when fast configuration is required, skip din because they should be pre-configured through programming reset/set */
if (fabric_bitstream.bit_din(bit_id) == bit_value_to_skip) { if (fast_configuration && fabric_bitstream.bit_din(bit_id) == bit_value_to_skip) {
continue; continue;
} }
/* Create string for BL address */ /* Create string for BL address */
@ -374,9 +375,10 @@ std::vector<std::string> reshape_bitstream_vectors_to_last_element(const std::ve
} }
MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_bitstream(const FabricBitstream& fabric_bitstream, MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_bitstream(const FabricBitstream& fabric_bitstream,
const bool& fast_configuration,
//const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks, //const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
const bool& bit_value_to_skip) { const bool& bit_value_to_skip) {
MemoryBankFlattenFabricBitstream raw_fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, bit_value_to_skip); MemoryBankFlattenFabricBitstream raw_fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip);
MemoryBankShiftRegisterFabricBitstream fabric_bits; MemoryBankShiftRegisterFabricBitstream fabric_bits;
/* Iterate over each word */ /* Iterate over each word */

2
openfpga/src/utils/fabric_bitstream_utils.h
View File

@ -62,6 +62,7 @@ size_t find_frame_based_fast_configuration_fabric_bitstream_size(const FabricBit
* @note the std::map may cause large memory footprint for large bitstream databases! * @note the std::map may cause large memory footprint for large bitstream databases!
*******************************************************************/ *******************************************************************/
MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(const FabricBitstream& fabric_bitstream, MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(const FabricBitstream& fabric_bitstream,
const bool& fast_configuration,
const bool& bit_value_to_skip); const bool& bit_value_to_skip);
/******************************************************************** /********************************************************************
@ -93,6 +94,7 @@ MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(cons
* @note the std::map may cause large memory footprint for large bitstream databases! * @note the std::map may cause large memory footprint for large bitstream databases!
*******************************************************************/ *******************************************************************/
MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_bitstream(const FabricBitstream& fabric_bitstream, MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_bitstream(const FabricBitstream& fabric_bitstream,
const bool& fast_configuration,
//const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks, //const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
const bool& bit_value_to_skip); const bool& bit_value_to_skip);