From 9e5debabe1782a5c343b131c1b20e33243a4efd5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 1 Oct 2021 16:23:38 -0700 Subject: [PATCH] [FPGA-Bitstream] Enable fast configuration for QuickLogic memory banks --- .../src/fpga_bitstream/write_text_fabric_bitstream.cpp | 8 ++++++-- openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 2 +- .../fpga_verilog/verilog_top_testbench_memory_bank.cpp | 1 + openfpga/src/utils/fabric_bitstream_utils.cpp | 8 +++++--- openfpga/src/utils/fabric_bitstream_utils.h | 2 ++ 5 files changed, 15 insertions(+), 6 deletions(-) diff --git a/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp index 399abbf28..257cb0e5b 100644 --- a/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp @@ -190,11 +190,12 @@ int write_memory_bank_fabric_bitstream_to_text_file(std::fstream& fp, *******************************************************************/ static int write_memory_bank_flatten_fabric_bitstream_to_text_file(std::fstream& fp, + const bool& fast_configuration, const bool& bit_value_to_skip, const FabricBitstream& fabric_bitstream) { int status = 0; - MemoryBankFlattenFabricBitstream fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, bit_value_to_skip); + MemoryBankFlattenFabricBitstream fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip); /* The address sizes and data input sizes are the same across any element, * just get it from the 1st element to save runtime @@ -234,11 +235,12 @@ int write_memory_bank_flatten_fabric_bitstream_to_text_file(std::fstream& fp, *******************************************************************/ static int write_memory_bank_shift_register_fabric_bitstream_to_text_file(std::fstream& fp, + const bool& fast_configuration, const bool& bit_value_to_skip, const FabricBitstream& fabric_bitstream) { int status = 0; - MemoryBankShiftRegisterFabricBitstream fabric_bits = build_memory_bank_shift_register_fabric_bitstream(fabric_bitstream, bit_value_to_skip); + MemoryBankShiftRegisterFabricBitstream fabric_bits = build_memory_bank_shift_register_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip); /* Output information about how to intepret the bitstream */ fp << "// Bitstream word count: " << fabric_bits.num_words() << std::endl; @@ -415,11 +417,13 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage fabric_bitstream); } else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) { status = write_memory_bank_flatten_fabric_bitstream_to_text_file(fp, + apply_fast_configuration, bit_value_to_skip, fabric_bitstream); } else { VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type()); status = write_memory_bank_shift_register_fabric_bitstream_to_text_file(fp, + apply_fast_configuration, bit_value_to_skip, fabric_bitstream); } diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index f3c9fcc54..0ef3eebcb 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -862,7 +862,7 @@ size_t calculate_num_config_clock_cycles(const ConfigProtocol& config_protocol, 100. * ((float)num_config_clock_cycles / (float)full_num_config_clock_cycles - 1.)); } } else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) { - num_config_clock_cycles = 1 + build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, bit_value_to_skip).size(); + num_config_clock_cycles = 1 + build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip).size(); } else if (BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type()) { /* TODO */ } diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp index 22c135743..7618cd510 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp @@ -187,6 +187,7 @@ void print_verilog_full_testbench_ql_memory_bank_flatten_bitstream(std::fstream& /* Reorganize the fabric bitstream by the same address across regions */ MemoryBankFlattenFabricBitstream fabric_bits_by_addr = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, + fast_configuration, bit_value_to_skip); /* Feed address and data input pair one by one diff --git a/openfpga/src/utils/fabric_bitstream_utils.cpp b/openfpga/src/utils/fabric_bitstream_utils.cpp index 448dc02ba..e09a99672 100644 --- a/openfpga/src/utils/fabric_bitstream_utils.cpp +++ b/openfpga/src/utils/fabric_bitstream_utils.cpp @@ -233,14 +233,15 @@ MemoryBankFabricBitstream build_memory_bank_fabric_bitstream_by_address(const Fa } MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(const FabricBitstream& fabric_bitstream, + const bool& fast_configuration, const bool& bit_value_to_skip) { /* Build the bitstream by each region, here we use (WL, BL) pairs when storing bitstreams */ vtr::vector> fabric_bits_per_region; fabric_bits_per_region.resize(fabric_bitstream.num_regions()); for (const FabricBitRegionId& region : fabric_bitstream.regions()) { for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) { - /* Skip din because they should be pre-configured through programming reset/set */ - if (fabric_bitstream.bit_din(bit_id) == bit_value_to_skip) { + /* Only when fast configuration is required, skip din because they should be pre-configured through programming reset/set */ + if (fast_configuration && fabric_bitstream.bit_din(bit_id) == bit_value_to_skip) { continue; } /* Create string for BL address */ @@ -374,9 +375,10 @@ std::vector reshape_bitstream_vectors_to_last_element(const std::ve } MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_bitstream(const FabricBitstream& fabric_bitstream, + const bool& fast_configuration, //const std::array& blwl_sr_banks, const bool& bit_value_to_skip) { - MemoryBankFlattenFabricBitstream raw_fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, bit_value_to_skip); + MemoryBankFlattenFabricBitstream raw_fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip); MemoryBankShiftRegisterFabricBitstream fabric_bits; /* Iterate over each word */ diff --git a/openfpga/src/utils/fabric_bitstream_utils.h b/openfpga/src/utils/fabric_bitstream_utils.h index 9a97a078b..b45db0c0d 100644 --- a/openfpga/src/utils/fabric_bitstream_utils.h +++ b/openfpga/src/utils/fabric_bitstream_utils.h @@ -62,6 +62,7 @@ size_t find_frame_based_fast_configuration_fabric_bitstream_size(const FabricBit * @note the std::map may cause large memory footprint for large bitstream databases! *******************************************************************/ MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(const FabricBitstream& fabric_bitstream, + const bool& fast_configuration, const bool& bit_value_to_skip); /******************************************************************** @@ -93,6 +94,7 @@ MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(cons * @note the std::map may cause large memory footprint for large bitstream databases! *******************************************************************/ MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_bitstream(const FabricBitstream& fabric_bitstream, + const bool& fast_configuration, //const std::array& blwl_sr_banks, const bool& bit_value_to_skip);