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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev

This commit is contained in:
ganeshgore 2020-04-24 21:30:51 -06:00
parent 773790bc2c 185e574738
commit 9e46b4eb75
28 changed files with 18 additions and 102 deletions
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13
openfpga/src/fpga_verilog/verilog_api.cpp
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@ -91,7 +91,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
*/
print_verilog_submodule(module_manager, netlist_manager,
mux_lib, circuit_lib,
src_dir_path, submodule_dir_path,
submodule_dir_path,
options);
/* Generate routing blocks */
@ -99,14 +99,14 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
print_verilog_unique_routing_modules(netlist_manager,
const_cast<const ModuleManager&>(module_manager),
device_rr_gsb,
src_dir_path, rr_dir_path,
rr_dir_path,
options.explicit_port_mapping());
} else {
VTR_ASSERT(false == options.compress_routing());
print_verilog_flatten_routing_modules(netlist_manager,
const_cast<const ModuleManager&>(module_manager),
device_rr_gsb,
src_dir_path, rr_dir_path,
rr_dir_path,
options.explicit_port_mapping());
}
@ -114,7 +114,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
print_verilog_grids(netlist_manager,
const_cast<const ModuleManager&>(module_manager),
device_ctx, device_annotation,
src_dir_path, lb_dir_path,
lb_dir_path,
options.explicit_port_mapping(),
options.verbose_output());
@ -180,8 +180,7 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager,
atom_ctx, place_ctx, io_location_map,
netlist_annotation,
netlist_name,
formal_verification_top_netlist_file_path,
src_dir_path);
formal_verification_top_netlist_file_path);
}
if (true == options.print_preconfig_top_testbench()) {
@ -190,7 +189,6 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager,
+ std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
print_verilog_random_top_testbench(netlist_name,
random_top_testbench_file_path,
src_dir_path,
atom_ctx,
netlist_annotation,
simulation_setting);
@ -208,7 +206,6 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager,
netlist_annotation,
netlist_name,
top_testbench_file_path,
src_dir_path,
simulation_setting);
}

3
openfpga/src/fpga_verilog/verilog_decoders.cpp
View File

@ -165,7 +165,6 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir) {
std::string verilog_fname(submodule_dir + std::string(LOCAL_ENCODER_VERILOG_FILE_NAME));
@ -181,8 +180,6 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
print_verilog_file_header(fp, "Local Decoders for Multiplexers");
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Create a library for local encoders with different sizes */
DecoderLibrary decoder_lib;

1
openfpga/src/fpga_verilog/verilog_decoders.h
View File

@ -25,7 +25,6 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir);
} /* end namespace openfpga */

3
openfpga/src/fpga_verilog/verilog_essential_gates.cpp
View File

@ -527,7 +527,6 @@ void print_verilog_constant_generator_module(const ModuleManager& module_manager
***********************************************/
void print_verilog_submodule_essentials(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const std::string& verilog_dir,
const std::string& submodule_dir,
const CircuitLibrary& circuit_lib) {
/* TODO: remove .bak when this part is completed and tested */
@ -546,8 +545,6 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
print_verilog_file_header(fp, "Essential gates");
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Print constant generators */
/* VDD */
print_verilog_constant_generator_module(module_manager, fp, 0);

1
openfpga/src/fpga_verilog/verilog_essential_gates.h
View File

@ -18,7 +18,6 @@ namespace openfpga {
void print_verilog_submodule_essentials(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const std::string& verilog_dir,
const std::string& submodule_dir,
const CircuitLibrary& circuit_lib);

6
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -183,7 +183,6 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
********************************************************************/
void print_verilog_random_top_testbench(const std::string& circuit_name,
const std::string& verilog_fname,
const std::string& verilog_dir,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const SimulationSetting& simulation_parameters) {
@ -203,11 +202,6 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
std::string title = std::string("FPGA Verilog Testbench for Formal Top-level netlist of Design: ") + circuit_name;
print_verilog_file_header(fp, title);
/* Print preprocessing flags and external netlists */
print_verilog_include_defines_preproc_file(fp, verilog_dir);
print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME)));
/* Preparation: find all the clock ports */
std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);

1
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h
View File

@ -17,7 +17,6 @@ namespace openfpga {
void print_verilog_random_top_testbench(const std::string& circuit_name,
const std::string& verilog_fname,
const std::string& verilog_dir,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const SimulationSetting& simulation_parameters);

15
openfpga/src/fpga_verilog/verilog_grid.cpp
View File

@ -197,7 +197,6 @@ static
void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const std::string& verilog_dir,
const std::string& subckt_dir,
t_pb_graph_node* pb_graph_head,
const bool& use_explicit_mapping,
@ -220,9 +219,6 @@ void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager,
print_verilog_file_header(fp, std::string("Verilog modules for logical tile: " + std::string(pb_graph_head->pb_type->name) + "]"));
/* Print preprocessing flags */
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Print Verilog modules for all the pb_types/pb_graph_nodes
* use a Depth-First Search Algorithm to print the sub-modules
* Note: DFS is the right way. Do NOT use BFS.
@ -262,7 +258,6 @@ void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager,
static
void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const std::string& verilog_dir,
const std::string& subckt_dir,
t_physical_tile_type_ptr phy_block_type,
const e_side& border_side,
@ -300,9 +295,6 @@ void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager,
print_verilog_file_header(fp, std::string("Verilog modules for physical tile: " + std::string(phy_block_type->name) + "]"));
/* Print preprocessing flags */
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Create a Verilog Module for the top-level physical block, and add to module manager */
std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_VERILOG_FILE_NAME_PREFIX), std::string(phy_block_type->name), is_io_type(phy_block_type), border_side);
ModuleId grid_module = module_manager.find_module(grid_module_name);
@ -338,7 +330,6 @@ void print_verilog_grids(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceContext& device_ctx,
const VprDeviceAnnotation& device_annotation,
const std::string& verilog_dir,
const std::string& subckt_dir,
const bool& use_explicit_mapping,
const bool& verbose) {
@ -362,7 +353,7 @@ void print_verilog_grids(NetlistManager& netlist_manager,
print_verilog_logical_tile_netlist(netlist_manager,
module_manager,
device_annotation,
verilog_dir, subckt_dir,
subckt_dir,
logical_tile.pb_graph_head,
use_explicit_mapping,
verbose);
@ -395,7 +386,7 @@ void print_verilog_grids(NetlistManager& netlist_manager,
for (const e_side& io_type_side : io_type_sides) {
print_verilog_physical_tile_netlist(netlist_manager,
module_manager,
verilog_dir, subckt_dir,
subckt_dir,
&physical_tile,
io_type_side,
use_explicit_mapping);
@ -405,7 +396,7 @@ void print_verilog_grids(NetlistManager& netlist_manager,
/* For CLB and heterogenenous blocks */
print_verilog_physical_tile_netlist(netlist_manager,
module_manager,
verilog_dir, subckt_dir,
subckt_dir,
&physical_tile,
NUM_SIDES,
use_explicit_mapping);

1
openfpga/src/fpga_verilog/verilog_grid.h
View File

@ -21,7 +21,6 @@ void print_verilog_grids(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceContext& device_ctx,
const VprDeviceAnnotation& device_annotation,
const std::string& verilog_dir,
const std::string& subckt_dir,
const bool& use_explicit_mapping,
const bool& verbose);

3
openfpga/src/fpga_verilog/verilog_lut.cpp
View File

@ -32,7 +32,6 @@ namespace openfpga {
void print_verilog_submodule_luts(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir,
const bool& use_explicit_port_map) {
std::string verilog_fname = submodule_dir + std::string(LUTS_VERILOG_FILE_NAME);
@ -50,8 +49,6 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
print_verilog_file_header(fp, "Look-Up Tables");
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Search for each LUT circuit model */
for (const auto& lut_model : circuit_lib.models()) {
/* Bypass user-defined and non-LUT modules */

1
openfpga/src/fpga_verilog/verilog_lut.h
View File

@ -21,7 +21,6 @@ namespace openfpga {
void print_verilog_submodule_luts(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir,
const bool& use_explicit_port_map);

3
openfpga/src/fpga_verilog/verilog_memory.cpp
View File

@ -100,7 +100,6 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir,
const bool& use_explicit_port_map) {
/* Plug in with the mux subckt */
@ -118,8 +117,6 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
print_verilog_file_header(fp, "Memories used in FPGA");
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Create the memory circuits for the multiplexer */
for (auto mux : mux_lib.muxes()) {
const MuxGraph& mux_graph = mux_lib.mux_graph(mux);

1
openfpga/src/fpga_verilog/verilog_memory.h
View File

@ -23,7 +23,6 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir,
const bool& use_explicit_port_map);

3
openfpga/src/fpga_verilog/verilog_mux.cpp
View File

@ -1227,7 +1227,6 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir,
const bool& use_explicit_port_map) {
@ -1245,8 +1244,6 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
print_verilog_file_header(fp, "Multiplexers");
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Generate basis sub-circuit for unique branches shared by the multiplexers */
for (auto mux : mux_lib.muxes()) {
const MuxGraph& mux_graph = mux_lib.mux_graph(mux);

1
openfpga/src/fpga_verilog/verilog_mux.h
View File

@ -24,7 +24,6 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir,
const bool& use_explicit_port_map);

8
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -385,8 +385,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,
const std::string& verilog_fname,
const std::string& verilog_dir) {
const std::string& verilog_fname) {
std::string timer_message = std::string("Write pre-configured FPGA top-level Verilog netlist for design '") + circuit_name + std::string("'");
/* Start time count */
@ -403,11 +402,6 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
std::string title = std::string("Verilog netlist for pre-configured FPGA fabric by design: ") + circuit_name;
print_verilog_file_header(fp, title);
/* Print preprocessing flags and external netlists */
print_verilog_include_defines_preproc_file(fp, verilog_dir);
print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME)));
/* Print module declaration and ports */
print_verilog_preconfig_top_module_ports(fp, circuit_name, atom_ctx, netlist_annotation);

3
openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
View File

@ -29,8 +29,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,
const std::string& verilog_fname,
const std::string& verilog_dir);
const std::string& verilog_fname);
} /* end namespace openfpga */

20
openfpga/src/fpga_verilog/verilog_routing.cpp
View File

@ -77,7 +77,6 @@ namespace openfpga {
static
void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const std::string& verilog_dir,
const std::string& subckt_dir,
const RRGSB& rr_gsb,
const t_rr_type& cb_type,
@ -94,9 +93,6 @@ void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_
print_verilog_file_header(fp, std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]"));
/* Print preprocessing flags */
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Create a Verilog Module based on the circuit model, and add to module manager */
ModuleId cb_module = module_manager.find_module(generate_connection_block_module_name(cb_type, gsb_coordinate));
VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
@ -182,7 +178,6 @@ void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_
static
void print_verilog_routing_switch_box_unique_module(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const std::string& verilog_dir,
const std::string& subckt_dir,
const RRGSB& rr_gsb,
const bool& use_explicit_port_map) {
@ -198,9 +193,6 @@ void print_verilog_routing_switch_box_unique_module(NetlistManager& netlist_mana
print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]"));
/* Print preprocessing flags */
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Create a Verilog Module based on the circuit model, and add to module manager */
ModuleId sb_module = module_manager.find_module(generate_switch_block_module_name(gsb_coordinate));
VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
@ -225,7 +217,6 @@ static
void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceRRGSB& device_rr_gsb,
const std::string& verilog_dir,
const std::string& subckt_dir,
const t_rr_type& cb_type,
const bool& use_explicit_port_map) {
@ -244,7 +235,6 @@ void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_mana
}
print_verilog_routing_connection_box_unique_module(netlist_manager,
module_manager,
verilog_dir,
subckt_dir,
rr_gsb, cb_type,
use_explicit_port_map);
@ -264,7 +254,6 @@ void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_mana
void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceRRGSB& device_rr_gsb,
const std::string& verilog_dir,
const std::string& subckt_dir,
const bool& use_explicit_port_map) {
/* Create a vector to contain all the Verilog netlist names that have been generated in this function */
@ -281,16 +270,15 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
}
print_verilog_routing_switch_box_unique_module(netlist_manager,
module_manager,
verilog_dir,
subckt_dir,
rr_gsb,
use_explicit_port_map);
}
}
print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map);
print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, subckt_dir, CHANX, use_explicit_port_map);
print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map);
print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, subckt_dir, CHANY, use_explicit_port_map);
/*
VTR_LOG("Writing header file for routing submodules '%s'...",
@ -317,7 +305,6 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceRRGSB& device_rr_gsb,
const std::string& verilog_dir,
const std::string& subckt_dir,
const bool& use_explicit_port_map) {
/* Create a vector to contain all the Verilog netlist names that have been generated in this function */
@ -328,7 +315,6 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
print_verilog_routing_switch_box_unique_module(netlist_manager,
module_manager,
verilog_dir,
subckt_dir,
unique_mirror,
use_explicit_port_map);
@ -340,7 +326,6 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
print_verilog_routing_connection_box_unique_module(netlist_manager,
module_manager,
verilog_dir,
subckt_dir,
unique_mirror, CHANX,
use_explicit_port_map);
@ -352,7 +337,6 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
print_verilog_routing_connection_box_unique_module(netlist_manager,
module_manager,
verilog_dir,
subckt_dir,
unique_mirror, CHANY,
use_explicit_port_map);

2
openfpga/src/fpga_verilog/verilog_routing.h
View File

@ -20,14 +20,12 @@ namespace openfpga {
void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceRRGSB& device_rr_gsb,
const std::string& verilog_dir,
const std::string& subckt_dir,
const bool& use_explicit_port_map);
void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceRRGSB& device_rr_gsb,
const std::string& verilog_dir,
const std::string& subckt_dir,
const bool& use_explicit_port_map);

14
openfpga/src/fpga_verilog/verilog_submodule.cpp
View File

@ -35,7 +35,6 @@ void print_verilog_submodule(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir,
const FabricVerilogOption& fpga_verilog_opts) {
@ -47,7 +46,6 @@ void print_verilog_submodule(ModuleManager& module_manager,
print_verilog_submodule_essentials(const_cast<const ModuleManager&>(module_manager),
netlist_manager,
verilog_dir,
submodule_dir,
circuit_lib);
@ -58,35 +56,35 @@ void print_verilog_submodule(ModuleManager& module_manager,
print_verilog_submodule_mux_local_decoders(const_cast<const ModuleManager&>(module_manager),
netlist_manager,
mux_lib, circuit_lib,
verilog_dir, submodule_dir);
submodule_dir);
print_verilog_submodule_muxes(module_manager, netlist_manager, mux_lib, circuit_lib,
verilog_dir, submodule_dir,
submodule_dir,
fpga_verilog_opts.explicit_port_mapping());
/* LUTes */
print_verilog_submodule_luts(const_cast<const ModuleManager&>(module_manager),
netlist_manager, circuit_lib,
verilog_dir, submodule_dir,
submodule_dir,
fpga_verilog_opts.explicit_port_mapping());
/* Hard wires */
print_verilog_submodule_wires(const_cast<const ModuleManager&>(module_manager),
netlist_manager, circuit_lib,
verilog_dir, submodule_dir);
submodule_dir);
/* 4. Memories */
print_verilog_submodule_memories(const_cast<const ModuleManager&>(module_manager),
netlist_manager,
mux_lib, circuit_lib,
verilog_dir, submodule_dir,
submodule_dir,
fpga_verilog_opts.explicit_port_mapping());
/* 5. Dump template for all the modules */
if (true == fpga_verilog_opts.print_user_defined_template()) {
print_verilog_submodule_templates(const_cast<const ModuleManager&>(module_manager),
circuit_lib,
verilog_dir, submodule_dir);
submodule_dir);
}
/* Create a header file to include all the subckts */

1
openfpga/src/fpga_verilog/verilog_submodule.h
View File

@ -20,7 +20,6 @@ void print_verilog_submodule(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir,
const FabricVerilogOption& fpga_verilog_opts);

3
openfpga/src/fpga_verilog/verilog_submodule_utils.cpp
View File

@ -207,7 +207,6 @@ void print_one_verilog_template_module(const ModuleManager& module_manager,
********************************************************************/
void print_verilog_submodule_templates(const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir) {
std::string verilog_fname(submodule_dir + USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME);
@ -223,8 +222,6 @@ void print_verilog_submodule_templates(const ModuleManager& module_manager,
print_verilog_file_header(fp, "Template for user-defined Verilog modules");
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Output essential models*/
for (const auto& model : circuit_lib.models()) {
/* Focus on user-defined modules, which must have a Verilog netlist defined */

1
openfpga/src/fpga_verilog/verilog_submodule_utils.h
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@ -29,7 +29,6 @@ void add_user_defined_verilog_modules(ModuleManager& module_manager,
void print_verilog_submodule_templates(const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir);
} /* end namespace openfpga */

3
openfpga/src/fpga_verilog/verilog_top_module.cpp
View File

@ -58,9 +58,6 @@ void print_verilog_top_module(NetlistManager& netlist_manager,
print_verilog_file_header(fp, std::string("Top-level Verilog module for FPGA"));
/* Print preprocessing flags */
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp, module_manager, top_module, use_explicit_mapping);

4
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
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@ -799,7 +799,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,
const std::string& verilog_fname,
const std::string& verilog_dir,
const SimulationSetting& simulation_parameters) {
std::string timer_message = std::string("Write autocheck testbench for FPGA top-level Verilog netlist for '") + circuit_name + std::string("'");
@ -818,9 +817,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
std::string title = std::string("FPGA Verilog Testbench for Top-level netlist of Design: ") + circuit_name;
print_verilog_file_header(fp, title);
/* Print preprocessing flags and external netlists */
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Find the top_module */
ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name());
VTR_ASSERT(true == module_manager.valid_module_id(top_module));

1
openfpga/src/fpga_verilog/verilog_top_testbench.h
View File

@ -33,7 +33,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,
const std::string& verilog_fname,
const std::string& verilog_dir,
const SimulationSetting& simulation_parameters);
} /* end namespace openfpga */

3
openfpga/src/fpga_verilog/verilog_wire.cpp
View File

@ -95,7 +95,6 @@ void print_verilog_wire_module(const ModuleManager& module_manager,
void print_verilog_submodule_wires(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir) {
std::string verilog_fname(submodule_dir + std::string(WIRES_VERILOG_FILE_NAME));
@ -111,8 +110,6 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager,
print_verilog_file_header(fp, "Wires");
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Print Verilog models for regular wires*/
print_verilog_comment(fp, std::string("----- BEGIN Verilog modules for regular wires -----"));
for (const auto& model : circuit_lib.models_by_type(CIRCUIT_MODEL_WIRE)) {

1
openfpga/src/fpga_verilog/verilog_wire.h
View File

@ -21,7 +21,6 @@ namespace openfpga {
void print_verilog_submodule_wires(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir);
} /* end namespace openfpga */