diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp index d2823df48..c8c7343ad 100644 --- a/openfpga/src/fpga_verilog/verilog_api.cpp +++ b/openfpga/src/fpga_verilog/verilog_api.cpp @@ -91,7 +91,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager, */ print_verilog_submodule(module_manager, netlist_manager, mux_lib, circuit_lib, - src_dir_path, submodule_dir_path, + submodule_dir_path, options); /* Generate routing blocks */ @@ -99,14 +99,14 @@ void fpga_fabric_verilog(ModuleManager& module_manager, print_verilog_unique_routing_modules(netlist_manager, const_cast(module_manager), device_rr_gsb, - src_dir_path, rr_dir_path, + rr_dir_path, options.explicit_port_mapping()); } else { VTR_ASSERT(false == options.compress_routing()); print_verilog_flatten_routing_modules(netlist_manager, const_cast(module_manager), device_rr_gsb, - src_dir_path, rr_dir_path, + rr_dir_path, options.explicit_port_mapping()); } @@ -114,7 +114,7 @@ void fpga_fabric_verilog(ModuleManager& module_manager, print_verilog_grids(netlist_manager, const_cast(module_manager), device_ctx, device_annotation, - src_dir_path, lb_dir_path, + lb_dir_path, options.explicit_port_mapping(), options.verbose_output()); @@ -180,8 +180,7 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager, atom_ctx, place_ctx, io_location_map, netlist_annotation, netlist_name, - formal_verification_top_netlist_file_path, - src_dir_path); + formal_verification_top_netlist_file_path); } if (true == options.print_preconfig_top_testbench()) { @@ -190,7 +189,6 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager, + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX); print_verilog_random_top_testbench(netlist_name, random_top_testbench_file_path, - src_dir_path, atom_ctx, netlist_annotation, simulation_setting); @@ -208,7 +206,6 @@ void fpga_verilog_testbench(const NetlistManager& netlist_manager, netlist_annotation, netlist_name, top_testbench_file_path, - src_dir_path, simulation_setting); } diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp index 0e993a3d3..30789e36f 100644 --- a/openfpga/src/fpga_verilog/verilog_decoders.cpp +++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp @@ -165,7 +165,6 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir) { std::string verilog_fname(submodule_dir + std::string(LOCAL_ENCODER_VERILOG_FILE_NAME)); @@ -181,8 +180,6 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana print_verilog_file_header(fp, "Local Decoders for Multiplexers"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Create a library for local encoders with different sizes */ DecoderLibrary decoder_lib; diff --git a/openfpga/src/fpga_verilog/verilog_decoders.h b/openfpga/src/fpga_verilog/verilog_decoders.h index f8d559f4d..9b2bbb6b1 100644 --- a/openfpga/src/fpga_verilog/verilog_decoders.h +++ b/openfpga/src/fpga_verilog/verilog_decoders.h @@ -25,7 +25,6 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp index 20be3e7e4..cb8eb9504 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp @@ -527,7 +527,6 @@ void print_verilog_constant_generator_module(const ModuleManager& module_manager ***********************************************/ void print_verilog_submodule_essentials(const ModuleManager& module_manager, NetlistManager& netlist_manager, - const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib) { /* TODO: remove .bak when this part is completed and tested */ @@ -546,8 +545,6 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager, print_verilog_file_header(fp, "Essential gates"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Print constant generators */ /* VDD */ print_verilog_constant_generator_module(module_manager, fp, 0); diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.h b/openfpga/src/fpga_verilog/verilog_essential_gates.h index b267d0e6e..2510e6d3d 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.h +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.h @@ -18,7 +18,6 @@ namespace openfpga { void print_verilog_submodule_essentials(const ModuleManager& module_manager, NetlistManager& netlist_manager, - const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib); diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index fa4f68938..8d4dab5c9 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -183,7 +183,6 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, ********************************************************************/ void print_verilog_random_top_testbench(const std::string& circuit_name, const std::string& verilog_fname, - const std::string& verilog_dir, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, const SimulationSetting& simulation_parameters) { @@ -203,11 +202,6 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, std::string title = std::string("FPGA Verilog Testbench for Formal Top-level netlist of Design: ") + circuit_name; print_verilog_file_header(fp, title); - /* Print preprocessing flags and external netlists */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME))); - /* Preparation: find all the clock ports */ std::vector clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h index 88692ae4f..b12072b70 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.h @@ -17,7 +17,6 @@ namespace openfpga { void print_verilog_random_top_testbench(const std::string& circuit_name, const std::string& verilog_fname, - const std::string& verilog_dir, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, const SimulationSetting& simulation_parameters); diff --git a/openfpga/src/fpga_verilog/verilog_grid.cpp b/openfpga/src/fpga_verilog/verilog_grid.cpp index 0cf509bde..d2917836b 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.cpp +++ b/openfpga/src/fpga_verilog/verilog_grid.cpp @@ -197,7 +197,6 @@ static void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager, const ModuleManager& module_manager, const VprDeviceAnnotation& device_annotation, - const std::string& verilog_dir, const std::string& subckt_dir, t_pb_graph_node* pb_graph_head, const bool& use_explicit_mapping, @@ -220,9 +219,6 @@ void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager, print_verilog_file_header(fp, std::string("Verilog modules for logical tile: " + std::string(pb_graph_head->pb_type->name) + "]")); - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Print Verilog modules for all the pb_types/pb_graph_nodes * use a Depth-First Search Algorithm to print the sub-modules * Note: DFS is the right way. Do NOT use BFS. @@ -262,7 +258,6 @@ void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager, static void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager, const ModuleManager& module_manager, - const std::string& verilog_dir, const std::string& subckt_dir, t_physical_tile_type_ptr phy_block_type, const e_side& border_side, @@ -300,9 +295,6 @@ void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager, print_verilog_file_header(fp, std::string("Verilog modules for physical tile: " + std::string(phy_block_type->name) + "]")); - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Create a Verilog Module for the top-level physical block, and add to module manager */ std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_VERILOG_FILE_NAME_PREFIX), std::string(phy_block_type->name), is_io_type(phy_block_type), border_side); ModuleId grid_module = module_manager.find_module(grid_module_name); @@ -338,7 +330,6 @@ void print_verilog_grids(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation, - const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_mapping, const bool& verbose) { @@ -362,7 +353,7 @@ void print_verilog_grids(NetlistManager& netlist_manager, print_verilog_logical_tile_netlist(netlist_manager, module_manager, device_annotation, - verilog_dir, subckt_dir, + subckt_dir, logical_tile.pb_graph_head, use_explicit_mapping, verbose); @@ -395,7 +386,7 @@ void print_verilog_grids(NetlistManager& netlist_manager, for (const e_side& io_type_side : io_type_sides) { print_verilog_physical_tile_netlist(netlist_manager, module_manager, - verilog_dir, subckt_dir, + subckt_dir, &physical_tile, io_type_side, use_explicit_mapping); @@ -405,7 +396,7 @@ void print_verilog_grids(NetlistManager& netlist_manager, /* For CLB and heterogenenous blocks */ print_verilog_physical_tile_netlist(netlist_manager, module_manager, - verilog_dir, subckt_dir, + subckt_dir, &physical_tile, NUM_SIDES, use_explicit_mapping); diff --git a/openfpga/src/fpga_verilog/verilog_grid.h b/openfpga/src/fpga_verilog/verilog_grid.h index 6d2843628..7603bd298 100644 --- a/openfpga/src/fpga_verilog/verilog_grid.h +++ b/openfpga/src/fpga_verilog/verilog_grid.h @@ -21,7 +21,6 @@ void print_verilog_grids(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation, - const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_mapping, const bool& verbose); diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp index fabe9340e..34767aff7 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.cpp +++ b/openfpga/src/fpga_verilog/verilog_lut.cpp @@ -32,7 +32,6 @@ namespace openfpga { void print_verilog_submodule_luts(const ModuleManager& module_manager, NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const bool& use_explicit_port_map) { std::string verilog_fname = submodule_dir + std::string(LUTS_VERILOG_FILE_NAME); @@ -50,8 +49,6 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager, print_verilog_file_header(fp, "Look-Up Tables"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Search for each LUT circuit model */ for (const auto& lut_model : circuit_lib.models()) { /* Bypass user-defined and non-LUT modules */ diff --git a/openfpga/src/fpga_verilog/verilog_lut.h b/openfpga/src/fpga_verilog/verilog_lut.h index e9ba3465a..a102e6df0 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.h +++ b/openfpga/src/fpga_verilog/verilog_lut.h @@ -21,7 +21,6 @@ namespace openfpga { void print_verilog_submodule_luts(const ModuleManager& module_manager, NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const bool& use_explicit_port_map); diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp index 53420a794..ad30eb337 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.cpp +++ b/openfpga/src/fpga_verilog/verilog_memory.cpp @@ -100,7 +100,6 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager, NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const bool& use_explicit_port_map) { /* Plug in with the mux subckt */ @@ -118,8 +117,6 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager, print_verilog_file_header(fp, "Memories used in FPGA"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Create the memory circuits for the multiplexer */ for (auto mux : mux_lib.muxes()) { const MuxGraph& mux_graph = mux_lib.mux_graph(mux); diff --git a/openfpga/src/fpga_verilog/verilog_memory.h b/openfpga/src/fpga_verilog/verilog_memory.h index a331e5687..f489df2ad 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.h +++ b/openfpga/src/fpga_verilog/verilog_memory.h @@ -23,7 +23,6 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager, NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const bool& use_explicit_port_map); diff --git a/openfpga/src/fpga_verilog/verilog_mux.cpp b/openfpga/src/fpga_verilog/verilog_mux.cpp index c85978722..3b7d3300b 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.cpp +++ b/openfpga/src/fpga_verilog/verilog_mux.cpp @@ -1227,7 +1227,6 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const bool& use_explicit_port_map) { @@ -1245,8 +1244,6 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, print_verilog_file_header(fp, "Multiplexers"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Generate basis sub-circuit for unique branches shared by the multiplexers */ for (auto mux : mux_lib.muxes()) { const MuxGraph& mux_graph = mux_lib.mux_graph(mux); diff --git a/openfpga/src/fpga_verilog/verilog_mux.h b/openfpga/src/fpga_verilog/verilog_mux.h index c98fa77d0..361c394dc 100644 --- a/openfpga/src/fpga_verilog/verilog_mux.h +++ b/openfpga/src/fpga_verilog/verilog_mux.h @@ -24,7 +24,6 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager, NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const bool& use_explicit_port_map); diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index 695d9275f..8e1de5cfc 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -385,8 +385,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, const IoLocationMap& io_location_map, const VprNetlistAnnotation& netlist_annotation, const std::string& circuit_name, - const std::string& verilog_fname, - const std::string& verilog_dir) { + const std::string& verilog_fname) { std::string timer_message = std::string("Write pre-configured FPGA top-level Verilog netlist for design '") + circuit_name + std::string("'"); /* Start time count */ @@ -403,11 +402,6 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, std::string title = std::string("Verilog netlist for pre-configured FPGA fabric by design: ") + circuit_name; print_verilog_file_header(fp, title); - /* Print preprocessing flags and external netlists */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - - print_verilog_include_netlist(fp, std::string(verilog_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME))); - /* Print module declaration and ports */ print_verilog_preconfig_top_module_ports(fp, circuit_name, atom_ctx, netlist_annotation); diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h index 499cafea9..e8efe5f29 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.h @@ -29,8 +29,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, const IoLocationMap& io_location_map, const VprNetlistAnnotation& netlist_annotation, const std::string& circuit_name, - const std::string& verilog_fname, - const std::string& verilog_dir); + const std::string& verilog_fname); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_routing.cpp b/openfpga/src/fpga_verilog/verilog_routing.cpp index 8f74c0074..e6df8e858 100644 --- a/openfpga/src/fpga_verilog/verilog_routing.cpp +++ b/openfpga/src/fpga_verilog/verilog_routing.cpp @@ -77,7 +77,6 @@ namespace openfpga { static void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_manager, const ModuleManager& module_manager, - const std::string& verilog_dir, const std::string& subckt_dir, const RRGSB& rr_gsb, const t_rr_type& cb_type, @@ -94,9 +93,6 @@ void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_ print_verilog_file_header(fp, std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]")); - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Create a Verilog Module based on the circuit model, and add to module manager */ ModuleId cb_module = module_manager.find_module(generate_connection_block_module_name(cb_type, gsb_coordinate)); VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); @@ -182,7 +178,6 @@ void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_ static void print_verilog_routing_switch_box_unique_module(NetlistManager& netlist_manager, const ModuleManager& module_manager, - const std::string& verilog_dir, const std::string& subckt_dir, const RRGSB& rr_gsb, const bool& use_explicit_port_map) { @@ -198,9 +193,6 @@ void print_verilog_routing_switch_box_unique_module(NetlistManager& netlist_mana print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]")); - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Create a Verilog Module based on the circuit model, and add to module manager */ ModuleId sb_module = module_manager.find_module(generate_switch_block_module_name(gsb_coordinate)); VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); @@ -225,7 +217,6 @@ static void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, - const std::string& verilog_dir, const std::string& subckt_dir, const t_rr_type& cb_type, const bool& use_explicit_port_map) { @@ -244,7 +235,6 @@ void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_mana } print_verilog_routing_connection_box_unique_module(netlist_manager, module_manager, - verilog_dir, subckt_dir, rr_gsb, cb_type, use_explicit_port_map); @@ -264,7 +254,6 @@ void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_mana void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, - const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_port_map) { /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ @@ -281,16 +270,15 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager, } print_verilog_routing_switch_box_unique_module(netlist_manager, module_manager, - verilog_dir, subckt_dir, rr_gsb, use_explicit_port_map); } } - print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map); + print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, subckt_dir, CHANX, use_explicit_port_map); - print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map); + print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, subckt_dir, CHANY, use_explicit_port_map); /* VTR_LOG("Writing header file for routing submodules '%s'...", @@ -317,7 +305,6 @@ void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager, void print_verilog_unique_routing_modules(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, - const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_port_map) { /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ @@ -328,7 +315,6 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager, const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb); print_verilog_routing_switch_box_unique_module(netlist_manager, module_manager, - verilog_dir, subckt_dir, unique_mirror, use_explicit_port_map); @@ -340,7 +326,6 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager, print_verilog_routing_connection_box_unique_module(netlist_manager, module_manager, - verilog_dir, subckt_dir, unique_mirror, CHANX, use_explicit_port_map); @@ -352,7 +337,6 @@ void print_verilog_unique_routing_modules(NetlistManager& netlist_manager, print_verilog_routing_connection_box_unique_module(netlist_manager, module_manager, - verilog_dir, subckt_dir, unique_mirror, CHANY, use_explicit_port_map); diff --git a/openfpga/src/fpga_verilog/verilog_routing.h b/openfpga/src/fpga_verilog/verilog_routing.h index a9f8fd6a1..9d439053a 100644 --- a/openfpga/src/fpga_verilog/verilog_routing.h +++ b/openfpga/src/fpga_verilog/verilog_routing.h @@ -20,14 +20,12 @@ namespace openfpga { void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, - const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_port_map); void print_verilog_unique_routing_modules(NetlistManager& netlist_manager, const ModuleManager& module_manager, const DeviceRRGSB& device_rr_gsb, - const std::string& verilog_dir, const std::string& subckt_dir, const bool& use_explicit_port_map); diff --git a/openfpga/src/fpga_verilog/verilog_submodule.cpp b/openfpga/src/fpga_verilog/verilog_submodule.cpp index b38750ab9..37df77c60 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule.cpp +++ b/openfpga/src/fpga_verilog/verilog_submodule.cpp @@ -35,7 +35,6 @@ void print_verilog_submodule(ModuleManager& module_manager, NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const FabricVerilogOption& fpga_verilog_opts) { @@ -47,7 +46,6 @@ void print_verilog_submodule(ModuleManager& module_manager, print_verilog_submodule_essentials(const_cast(module_manager), netlist_manager, - verilog_dir, submodule_dir, circuit_lib); @@ -58,35 +56,35 @@ void print_verilog_submodule(ModuleManager& module_manager, print_verilog_submodule_mux_local_decoders(const_cast(module_manager), netlist_manager, mux_lib, circuit_lib, - verilog_dir, submodule_dir); + submodule_dir); print_verilog_submodule_muxes(module_manager, netlist_manager, mux_lib, circuit_lib, - verilog_dir, submodule_dir, + submodule_dir, fpga_verilog_opts.explicit_port_mapping()); /* LUTes */ print_verilog_submodule_luts(const_cast(module_manager), netlist_manager, circuit_lib, - verilog_dir, submodule_dir, + submodule_dir, fpga_verilog_opts.explicit_port_mapping()); /* Hard wires */ print_verilog_submodule_wires(const_cast(module_manager), netlist_manager, circuit_lib, - verilog_dir, submodule_dir); + submodule_dir); /* 4. Memories */ print_verilog_submodule_memories(const_cast(module_manager), netlist_manager, mux_lib, circuit_lib, - verilog_dir, submodule_dir, + submodule_dir, fpga_verilog_opts.explicit_port_mapping()); /* 5. Dump template for all the modules */ if (true == fpga_verilog_opts.print_user_defined_template()) { print_verilog_submodule_templates(const_cast(module_manager), circuit_lib, - verilog_dir, submodule_dir); + submodule_dir); } /* Create a header file to include all the subckts */ diff --git a/openfpga/src/fpga_verilog/verilog_submodule.h b/openfpga/src/fpga_verilog/verilog_submodule.h index d3de8b9d7..06bb7aeef 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule.h +++ b/openfpga/src/fpga_verilog/verilog_submodule.h @@ -20,7 +20,6 @@ void print_verilog_submodule(ModuleManager& module_manager, NetlistManager& netlist_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir, const FabricVerilogOption& fpga_verilog_opts); diff --git a/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp index b4255b3e9..faf965068 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_submodule_utils.cpp @@ -207,7 +207,6 @@ void print_one_verilog_template_module(const ModuleManager& module_manager, ********************************************************************/ void print_verilog_submodule_templates(const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir) { std::string verilog_fname(submodule_dir + USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME); @@ -223,8 +222,6 @@ void print_verilog_submodule_templates(const ModuleManager& module_manager, print_verilog_file_header(fp, "Template for user-defined Verilog modules"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Output essential models*/ for (const auto& model : circuit_lib.models()) { /* Focus on user-defined modules, which must have a Verilog netlist defined */ diff --git a/openfpga/src/fpga_verilog/verilog_submodule_utils.h b/openfpga/src/fpga_verilog/verilog_submodule_utils.h index fedcb63a8..3f0e1dadd 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule_utils.h +++ b/openfpga/src/fpga_verilog/verilog_submodule_utils.h @@ -29,7 +29,6 @@ void add_user_defined_verilog_modules(ModuleManager& module_manager, void print_verilog_submodule_templates(const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_top_module.cpp b/openfpga/src/fpga_verilog/verilog_top_module.cpp index 9596f20a3..79c6ebebe 100644 --- a/openfpga/src/fpga_verilog/verilog_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_module.cpp @@ -58,9 +58,6 @@ void print_verilog_top_module(NetlistManager& netlist_manager, print_verilog_file_header(fp, std::string("Top-level Verilog module for FPGA")); - /* Print preprocessing flags */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Write the module content in Verilog format */ write_verilog_module_to_file(fp, module_manager, top_module, use_explicit_mapping); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 25017d741..a477fa99e 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -799,7 +799,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, const VprNetlistAnnotation& netlist_annotation, const std::string& circuit_name, const std::string& verilog_fname, - const std::string& verilog_dir, const SimulationSetting& simulation_parameters) { std::string timer_message = std::string("Write autocheck testbench for FPGA top-level Verilog netlist for '") + circuit_name + std::string("'"); @@ -818,9 +817,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, std::string title = std::string("FPGA Verilog Testbench for Top-level netlist of Design: ") + circuit_name; print_verilog_file_header(fp, title); - /* Print preprocessing flags and external netlists */ - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Find the top_module */ ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name()); VTR_ASSERT(true == module_manager.valid_module_id(top_module)); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h index 5684b37e2..c0ad77c51 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.h +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h @@ -33,7 +33,6 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, const VprNetlistAnnotation& netlist_annotation, const std::string& circuit_name, const std::string& verilog_fname, - const std::string& verilog_dir, const SimulationSetting& simulation_parameters); } /* end namespace openfpga */ diff --git a/openfpga/src/fpga_verilog/verilog_wire.cpp b/openfpga/src/fpga_verilog/verilog_wire.cpp index d28b26f81..bb8419edd 100644 --- a/openfpga/src/fpga_verilog/verilog_wire.cpp +++ b/openfpga/src/fpga_verilog/verilog_wire.cpp @@ -95,7 +95,6 @@ void print_verilog_wire_module(const ModuleManager& module_manager, void print_verilog_submodule_wires(const ModuleManager& module_manager, NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir) { std::string verilog_fname(submodule_dir + std::string(WIRES_VERILOG_FILE_NAME)); @@ -111,8 +110,6 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager, print_verilog_file_header(fp, "Wires"); - print_verilog_include_defines_preproc_file(fp, verilog_dir); - /* Print Verilog models for regular wires*/ print_verilog_comment(fp, std::string("----- BEGIN Verilog modules for regular wires -----")); for (const auto& model : circuit_lib.models_by_type(CIRCUIT_MODEL_WIRE)) { diff --git a/openfpga/src/fpga_verilog/verilog_wire.h b/openfpga/src/fpga_verilog/verilog_wire.h index 62331d8b9..d9996fbcf 100644 --- a/openfpga/src/fpga_verilog/verilog_wire.h +++ b/openfpga/src/fpga_verilog/verilog_wire.h @@ -21,7 +21,6 @@ namespace openfpga { void print_verilog_submodule_wires(const ModuleManager& module_manager, NetlistManager& netlist_manager, const CircuitLibrary& circuit_lib, - const std::string& verilog_dir, const std::string& submodule_dir); } /* end namespace openfpga */