riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

minor change to task.conf to check CI

This commit is contained in:
coolbreeze413 2021-11-19 18:49:37 +05:30
parent b86bd1ca68
commit 9ca8ab4fa2
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
View File

@ -23,6 +23,7 @@ openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/task
openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/pin_constraints.xml
yosys_args = -no_adder -family qlf_k4n8 -no_ff_map yosys_args = -no_adder -family qlf_k4n8 -no_ff_map
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile8Clk_40nm.xml