[arch language] Now circuit library will automatically identify the default circuit model if needed
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@ -2,6 +2,7 @@
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#include <algorithm>
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#include <algorithm>
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#include "vtr_assert.h"
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "openfpga_port_parser.h"
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#include "openfpga_port_parser.h"
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#include "circuit_library.h"
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#include "circuit_library.h"
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@ -2108,6 +2109,23 @@ void CircuitLibrary::build_timing_graphs() {
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return;
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return;
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}
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}
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/* Automatically identify the default models for each type*/
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void CircuitLibrary::auto_detect_default_models() {
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/* Go through the model fast look-up */
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for (const auto& curr_type_models : model_lookup_) {
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if ( (1 == curr_type_models.size())
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&& (false == model_is_default(curr_type_models[0]))) {
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/* This is the only model in this type,
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* it is safe to set it to be default
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* Give a warning for users
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*/
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set_model_is_default(curr_type_models[0], true);
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VTR_LOG_WARN("Automatically set circuit model '%s' to be default in its type.\n",
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model_name(curr_type_models[0]).c_str());
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}
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}
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}
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/************************************************************************
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/************************************************************************
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* Internal mutators: build timing graphs
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* Internal mutators: build timing graphs
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***********************************************************************/
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***********************************************************************/
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@ -461,6 +461,10 @@ class CircuitLibrary {
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public: /* Public Mutators: builders */
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public: /* Public Mutators: builders */
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void build_model_links();
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void build_model_links();
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void build_timing_graphs();
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void build_timing_graphs();
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/* Automatically identify the default models for each type,
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* suggest to do this after circuit library is built
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*/
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void auto_detect_default_models();
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public: /* Internal mutators: build timing graphs */
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public: /* Internal mutators: build timing graphs */
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void add_edge(const CircuitModelId& model_id,
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void add_edge(const CircuitModelId& model_id,
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const CircuitPortId& from_port, const size_t& from_pin,
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const CircuitPortId& from_port, const size_t& from_pin,
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@ -52,6 +52,9 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
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auto xml_circuit_models = get_single_child(xml_openfpga_arch, "circuit_library", loc_data);
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auto xml_circuit_models = get_single_child(xml_openfpga_arch, "circuit_library", loc_data);
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openfpga_arch.circuit_lib = read_xml_circuit_library(xml_circuit_models, loc_data);
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openfpga_arch.circuit_lib = read_xml_circuit_library(xml_circuit_models, loc_data);
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/* Automatically identify the default models for circuit library */
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openfpga_arch.circuit_lib.auto_detect_default_models();
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/* Build the internal links for the circuit library */
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/* Build the internal links for the circuit library */
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openfpga_arch.circuit_lib.build_model_links();
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openfpga_arch.circuit_lib.build_model_links();
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