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[Test] Add a new test case to valid the architecture using 4 clock in different ports

This commit is contained in:
tangxifan 2022-03-20 10:18:00 +08:00
parent b2d96e18df
commit 9a731cdca0
5 changed files with 95 additions and 0 deletions
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11
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/and2_latch_pin_constraints.xml Normal file
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<pin_constraints>
<!-- For a given .blif file, we want to assign
- the clk0 signal to the clk[0] port of the FPGA fabric
- the clk1 signal to the clk[1] port of the FPGA fabric
-->
<set_io pin="clk0" net="clk0"/>
<set_io pin="clk1" net="clk1"/>
<set_io pin="clk2" net="OPEN"/>
<set_io pin="clk3" net="OPEN"/>
</pin_constraints>

14
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/and2_latch_repack_pin_constraints.xml Normal file
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<repack_design_constraints>
<!-- For a given .blif file, we want to assign
- the clk0 signal to the clk[0] port of all the clb tiles available in the FPGA fabric
- the clk1 signal to the clk[1] port of all the clb tiles available in the FPGA fabric
and ensure no signals could be mapped to
- the clk[2] port of all the clb tiles available in the FPGA fabric
- the clk[3] port of all the clb tiles available in the FPGA fabric
-->
<pin_constraint pb_type="clb" pin="clk0" net="clk0"/>
<pin_constraint pb_type="clb" pin="clk1" net="clk1"/>
<pin_constraint pb_type="clb" pin="clk2" net="OPEN"/>
<pin_constraint pb_type="clb" pin="clk3" net="OPEN"/>
</repack_design_constraints>

12
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/counter_2clock_pin_constraints.xml Normal file
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<pin_constraints>
<!-- For a given .blif file, we want to assign
- the clk0 signal to the clk[0] port of the FPGA fabric
- the clk1 signal to the clk[1] port of the FPGA fabric
-->
<set_io pin="clk0" net="clk0"/>
<set_io pin="clk1" net="clk1"/>
<set_io pin="clk2" net="OPEN"/>
<set_io pin="clk3" net="OPEN"/>
<set_io pin="reset[0]" net="rst"/>
</pin_constraints>

14
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/counter_2clock_repack_pin_constraints.xml Normal file
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<repack_design_constraints>
<!-- For a given .blif file, we want to assign
- the clk0 signal to the clk[0] port of all the clb tiles available in the FPGA fabric
- the clk1 signal to the clk[1] port of all the clb tiles available in the FPGA fabric
and ensure no signals could be mapped to
- the clk[2] port of all the clb tiles available in the FPGA fabric
- the clk[3] port of all the clb tiles available in the FPGA fabric
-->
<pin_constraint pb_type="clb" pin="clk0" net="clk0"/>
<pin_constraint pb_type="clb" pin="clk1" net="clk1"/>
<pin_constraint pb_type="clb" pin="clk2" net="OPEN"/>
<pin_constraint pb_type="clb" pin="clk3" net="OPEN"/>
</repack_design_constraints>

44
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/task.conf Normal file
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4ClkPort_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_4clock_sim_openfpga.xml
openfpga_repack_design_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4ClkPort_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch_2clock/and2_latch_2clock.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = counter_4bit_2clock
bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/counter_2clock_pin_constraints.xml
bench0_openfpga_repack_design_constraints_file=${PATH:TASK_DIR}/config/counter_2clock_repack_pin_constraints.xml
bench1_top = and2_latch_2clock
bench1_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/and2_latch_pin_constraints.xml
bench1_openfpga_repack_design_constraints_file=${PATH:TASK_DIR}/config/and2_latch_repack_pin_constraints.xml
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=