From 9a731cdca07aac6929ca413975bd4336843a1396 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 20 Mar 2022 10:18:00 +0800 Subject: [PATCH] [Test] Add a new test case to valid the architecture using 4 clock in different ports --- .../config/and2_latch_pin_constraints.xml | 11 +++++ .../and2_latch_repack_pin_constraints.xml | 14 ++++++ .../config/counter_2clock_pin_constraints.xml | 12 +++++ .../counter_2clock_repack_pin_constraints.xml | 14 ++++++ .../global_tile_4clockport/config/task.conf | 44 +++++++++++++++++++ 5 files changed, 95 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/and2_latch_pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/and2_latch_repack_pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/counter_2clock_pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/counter_2clock_repack_pin_constraints.xml create mode 100644 openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/and2_latch_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/and2_latch_pin_constraints.xml new file mode 100644 index 000000000..b4c931f20 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/and2_latch_pin_constraints.xml @@ -0,0 +1,11 @@ + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/and2_latch_repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/and2_latch_repack_pin_constraints.xml new file mode 100644 index 000000000..a284a2aaf --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/and2_latch_repack_pin_constraints.xml @@ -0,0 +1,14 @@ + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/counter_2clock_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/counter_2clock_pin_constraints.xml new file mode 100644 index 000000000..57841bb64 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/counter_2clock_pin_constraints.xml @@ -0,0 +1,12 @@ + + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/counter_2clock_repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/counter_2clock_repack_pin_constraints.xml new file mode 100644 index 000000000..a284a2aaf --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/counter_2clock_repack_pin_constraints.xml @@ -0,0 +1,14 @@ + + + + + + + + diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/task.conf new file mode 100644 index 000000000..204d587fc --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clockport/config/task.conf @@ -0,0 +1,44 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_multiclock_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4ClkPort_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_4clock_sim_openfpga.xml +openfpga_repack_design_constraints_file=${PATH:TASK_DIR}/config/repack_pin_constraints.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4ClkPort_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch_2clock/and2_latch_2clock.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches + +bench0_top = counter_4bit_2clock +bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/counter_2clock_pin_constraints.xml +bench0_openfpga_repack_design_constraints_file=${PATH:TASK_DIR}/config/counter_2clock_repack_pin_constraints.xml + +bench1_top = and2_latch_2clock +bench1_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/and2_latch_pin_constraints.xml +bench1_openfpga_repack_design_constraints_file=${PATH:TASK_DIR}/config/and2_latch_repack_pin_constraints.xml + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist=