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light change on arch file to accelerate mcnc big20 run

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tangxifan 2020-04-19 12:03:31 -06:00
parent cc163081f5
commit 98878f474b
1 changed files with 1 additions and 1 deletions
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openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
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@ -73,7 +73,7 @@
make it physically equivalent on all sides so that only one definition of I/Os is needed. make it physically equivalent on all sides so that only one definition of I/Os is needed.
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
--> -->
<tile name="io" capacity="1" area="0"> <tile name="io" capacity="8" area="0">
<equivalent_sites> <equivalent_sites>
<site pb_type="io"/> <site pb_type="io"/>
</equivalent_sites> </equivalent_sites>