From 98878f474b04270527d88356bc285bf8f91c616d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 19 Apr 2020 12:03:31 -0600
Subject: [PATCH] light change on arch file to accelerate mcnc big20 run

---
 ...frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
index 1b51c45af..174649d93 100755
--- a/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
+++ b/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
@@ -73,7 +73,7 @@
          make it physically equivalent on all sides so that only one definition of I/Os is needed.
          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
       -->
-    <tile name="io" capacity="1" area="0">
+    <tile name="io" capacity="8" area="0">
       <equivalent_sites>
         <site pb_type="io"/>
       </equivalent_sites>