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[Test] Typo fix

This commit is contained in:
tangxifan 2022-01-31 13:03:45 -08:00
parent da8fc0f5d4
commit 9871fe88fb
1 changed files with 1 additions and 1 deletions
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openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
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@ -145,4 +145,4 @@ run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_none --debug --sho
run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim --debug --show_thread_logs run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim --debug --show_thread_logs
echo -e "Testing the netlist generation by forcing the use of relative paths"; echo -e "Testing the netlist generation by forcing the use of relative paths";
run-task fpga_verilog/verilog_netlist_formats/use_relative_path--debug --show_thread_logs run-task fpga_verilog/verilog_netlist_formats/use_relative_path --debug --show_thread_logs