From 9871fe88fb123c9d86bcd9ff173a10d26737b901 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 31 Jan 2022 13:03:45 -0800 Subject: [PATCH] [Test] Typo fix --- openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh index 0a396b70c..7d781e7be 100755 --- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh @@ -145,4 +145,4 @@ run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_none --debug --sho run-task fpga_verilog/verilog_netlist_formats/embed_bitstream_modelsim --debug --show_thread_logs echo -e "Testing the netlist generation by forcing the use of relative paths"; -run-task fpga_verilog/verilog_netlist_formats/use_relative_path--debug --show_thread_logs +run-task fpga_verilog/verilog_netlist_formats/use_relative_path --debug --show_thread_logs