Merge pull request #21 from RapidSilicon/qlbank_sr
Now QuickLogic Memory Bank Supports WLR signal in shift register-based protocols
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tangxifan
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@ -167,10 +167,39 @@ The BL and WL protocols can be customized through the XML syntax ``bl`` and ``wl
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</organization>
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</configuration_protocol>
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.. option:: protocol="decoder|flatten"
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.. option:: protocol="decoder|flatten|shift_register"
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- ``decoder``: BLs or WLs are controlled by decoders with address lines. For BLs, the decoder includes an enable signal as well as a data input signal. This is the default option if not specified.
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- ``flatten``: BLs or WLs are directly available at the FPGA fabric. In this way, all the configurable memorys on the same WL can be written through the BL signals in one clock cycle
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- ``decoder``: BLs or WLs are controlled by decoders with address lines. For BLs, the decoder includes an enable signal as well as a data input signal. This is the default option if not specified. See an illustrative example in :numref:`fig_memory_bank_decoder_based`.
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- ``flatten``: BLs or WLs are directly available at the FPGA fabric. In this way, all the configurable memorys on the same WL can be written through the BL signals in one clock cycle. See an illustrative example in :numref:`fig_memory_bank_flatten`.
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- ``shift_register``: BLs or WLs are controlled by shift register chains. The BL/WLs are programming each time the shift register chains are fully loaded. See an illustrative example in :numref:`fig_memory_bank_shift_register`.
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.. _fig_memory_bank_decoder_based:
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.. figure:: figures/memory_bank_decoder.svg
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:scale: 30%
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:alt: map to buried treasure
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Example of (a) a memory organization using address decoders; (b) single memory bank across the fabric; and (c) multiple memory banks across the fabric.
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.. _fig_memory_bank_flatten:
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.. figure:: figures/memory_bank_flatten.svg
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:scale: 30%
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:alt: map to buried treasure
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Example of (a) a memory organization with direct access to BL/WL signals; (b) single memory bank across the fabric; and (c) multiple memory banks across the fabric.
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.. _fig_memory_bank_shift_register:
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.. figure:: figures/memory_bank_shift_register.svg
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:scale: 30%
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:alt: map to buried treasure
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Example of (a) a memory organization using shift register chains to control BL/WLs; (b) single memory bank across the fabric; and (c) multiple memory banks across the fabric.
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.. note:: The flip-flop for WL shift register requires an enable signal to gate WL signals when loading WL shift registers
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.. note:: Memory-bank decoders does require a memory cell to have
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@ -65,6 +65,112 @@ The information depends on the type of configuration procotol.
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.. note:: When there are multiple configuration regions, each ``<bit_value>`` may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively.
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.. option:: ql_memory_bank using decoders
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Multiple lines will be included, each of which is organized as <bl_address><wl_address><bits>.
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The size of address line and data input bits are shown as a comment in the bitstream file, which eases the development of bitstream downloader.
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For example
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.. code-block:: verilog
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// Bitstream width (LSB -> MSB): <bl_address 5 bits><wl_address 5 bits><data input 1 bits>
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The first part represents the Bit-Line address.
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The second part represents the Word-Line address.
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The third part represents the configuration bit.
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For example
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.. code-block:: xml
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<bitline_address><wordline_address><bit_value>
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<bitline_address><wordline_address><bit_value>
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...
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<bitline_address><wordline_address><bit_value>
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.. note:: When there are multiple configuration regions, each ``<bit_value>`` may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively.
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.. option:: ql_memory_bank using flatten BL and WLs
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Multiple lines will be included, each of which is organized as <bl_data><wl_data>.
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The size of data are shown as a comment in the bitstream file, which eases the development of bitstream downloader.
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For example
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.. code-block:: verilog
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// Bitstream width (LSB -> MSB): <Region 1: bl_data 5 bits><Region 2: bl_data 4 bits><Region 1: wl_data 5 bits><Region 2: wl_data 6 bits>
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The first part represents the Bit-Line data from multiple configuration regions.
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The second part represents the Word-Line data from multiple configuration regions.
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For example
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.. code-block:: xml
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<bitline_data_region1><bitline_data_region2><wordline_data_region1><wordline_data_region2>
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<bitline_data_region1><bitline_data_region2><wordline_data_region1><wordline_data_region2>
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...
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<bitline_data_region1><bitline_data_region2><wordline_data_region1><wordline_data_region2>
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.. note:: The WL data of region is one-hot.
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.. option:: ql_memory_bank using shift registers
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Multiple lines will be included, each of which is organized as <bl_data> or <wl_data>.
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The size of data are shown as a comment in the bitstream file, which eases the development of bitstream downloader.
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For example
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.. code-block:: verilog
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// Bitstream word count: 36
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// Bitstream bl word size: 39
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// Bitstream wl word size: 37
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// Bitstream width (LSB -> MSB): <bl shift register heads 1 bits><wl shift register heads 1 bits>
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The bitstream data are organized by words. Each word consists of two parts, BL data to be loaded to BL shift register chains and WL data to be loaded to WL shift register chains
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For example
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.. code-block:: xml
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// Word 0
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// BL Part
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<bitline_shift_register_data@clock_0> ----
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<bitline_shift_register_data@clock_1> ^
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<bitline_shift_register_data@clock_1> |
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... BL word size
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<bitline_shift_register_data@clock_n-2> |
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<bitline_shift_register_data@clock_n-1> v
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<bitline_shift_register_data@clock_n> ----
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// Word 0
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// WL Part
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<wordline_shift_register_data@clock_0> ----
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<wordline_shift_register_data@clock_1> ^
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<wordline_shift_register_data@clock_1> |
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... WL word size
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<wordline_shift_register_data@clock_n-2> |
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<wordline_shift_register_data@clock_n-1> v
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<wordline_shift_register_data@clock_n> ----
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// Word 1
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// BL Part
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<bitline_shift_register_data@clock_0> ----
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<bitline_shift_register_data@clock_1> ^
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<bitline_shift_register_data@clock_1> |
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... BL word size
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<bitline_shift_register_data@clock_n-2> |
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<bitline_shift_register_data@clock_n-1> v
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<bitline_shift_register_data@clock_n> ----
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// Word 1
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// WL Part
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<wordline_shift_register_data@clock_0> ----
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<wordline_shift_register_data@clock_1> ^
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<wordline_shift_register_data@clock_1> |
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... WL word size
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<wordline_shift_register_data@clock_n-2> |
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<wordline_shift_register_data@clock_n-1> v
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<wordline_shift_register_data@clock_n> ----
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... // More words
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.. note:: The BL/WL data may be multi-bit, while each bit corresponds to a configuration region
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.. note:: The WL data of region is one-hot.
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.. option:: frame_based
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Multiple lines will be included, each of which is organized as ``<address><data_input_bits>``.
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@ -301,11 +301,18 @@ ModuleId build_wl_shift_register_chain_module(ModuleManager& module_manager,
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circuit_lib.port_size(sram_output_ports[0]));
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module_manager.add_port(mem_module, chain_tail_port, ModuleManager::MODULE_OUTPUT_PORT);
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/* Add the output ports to output BL signals */
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/* Add the output ports to output BL/WL signals */
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BasicPort chain_wl_port(WL_SHIFT_REGISTER_CHAIN_WL_OUT_NAME,
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num_mems);
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module_manager.add_port(mem_module, chain_wl_port, ModuleManager::MODULE_OUTPUT_PORT);
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/* Add the output ports to output WLR signals */
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if (!sram_wlr_ports.empty()) {
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BasicPort chain_wlr_port(WL_SHIFT_REGISTER_CHAIN_WLR_OUT_NAME,
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num_mems);
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module_manager.add_port(mem_module, chain_wlr_port, ModuleManager::MODULE_OUTPUT_PORT);
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}
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/* Find the sram module in the module manager */
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ModuleId sram_mem_module = module_manager.find_module(circuit_lib.model_name(sram_model));
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@ -166,11 +166,11 @@
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<port type="output" prefix="inpad" lib_name="Y" size="1"/>
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</circuit_model>
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<!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
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<circuit_model type="ccff" name="BL_DFFRQ" prefix="BL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<circuit_model type="ccff" name="BL_DFFRQ" prefix="BL_DFFRQ" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true" is_shift_register="true"/>
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<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="D" lib_name="SIN" size="1"/>
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<port type="output" prefix="Q" lib_name="SOUT" size="1"/>
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<port type="bl" prefix="BL" lib_name="BL" size="1"/>
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@ -181,7 +181,7 @@
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true" is_shift_register="true"/>
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<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="D" lib_name="SIN" size="1"/>
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<port type="output" prefix="Q" lib_name="SOUT" size="1"/>
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<port type="wl" prefix="wl" lib_name="WLW" size="1"/>
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@ -60,6 +60,7 @@ run-task basic_tests/full_testbench/multi_region_ql_memory_bank --debug --show_t
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run-task basic_tests/full_testbench/ql_memory_bank_flatten --debug --show_thread_logs
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run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr --debug --show_thread_logs
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run-task basic_tests/full_testbench/ql_memory_bank_shift_register --debug --show_thread_logs
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run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr --debug --show_thread_logs
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echo -e "Testing testbenches without self checking features";
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run-task basic_tests/full_testbench/full_testbench_without_self_checking --debug --show_thread_logs
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@ -0,0 +1,45 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_wlr_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_shift_register_sim_openfpga.xml
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openfpga_vpr_device_layout=
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openfpga_fast_configuration=
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
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bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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bench0_chan_width = 300
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bench1_top = or2
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bench1_chan_width = 300
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bench2_top = and2_latch
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bench2_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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