Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring

.travis/script.sh

@@ -12,6 +12,8 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
   cd build
   cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off 
   make -j16
+  alias python3.5="python3"
+  ln -s /opt/local/bin/python3 /opt/loca/bin/python3.5
 else
 # For linux, we enable full package compilation
   #make

openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml

@@ -290,7 +290,7 @@
         <port type="sram" prefix="sram" size="1"/>
       </circuit_model>
       <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-      <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerlogNetlists/ff.v">
+      <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
          <design_technology type="cmos"/>
          <input_buffer exist="on" circuit_model_name="INVTX1"/>
          <output_buffer exist="on" circuit_model_name="INVTX1"/>
@@ -362,7 +362,7 @@
         <port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
       </circuit_model>
       <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-      <circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerlogNetlists/ff.v">
+      <circuit_model type="sff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
          <design_technology type="cmos"/>
          <input_buffer exist="on" circuit_model_name="INVTX1"/>
          <output_buffer exist="on" circuit_model_name="INVTX1"/>

openfpga_flow/scripts/run_fpga_flow.py

@@ -215,10 +215,10 @@ def main():
     if (args.fpga_flow == "yosys_vpr"):
         logger.info('Running "yosys_vpr" Flow')
         run_yosys_with_abc()
-        run_rewrite_verilog()
         if args.power:
             run_ace2()
             run_pro_blif_3arg()
+        run_rewrite_verilog()
     if (args.fpga_flow == "vpr_blif"):
         collect_files_for_vpr()
     # if (args.fpga_flow == "vtr"):
@@ -741,7 +741,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
                             process.returncode)
     except (Exception, subprocess.CalledProcessError) as e:
         logger.exception("Failed to run VPR")
-        process_failed_vpr_run(e.output)
+        filter_failed_process_output(e.output)
         clean_up_and_exit("")
     logger.info("VPR output is written in file %s" % logfile)
     return chan_width
@@ -796,22 +796,7 @@ def run_rewrite_verilog():
         "write_verilog %s" % args.top_module+"_output_verilog.v"
     ]
     command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)]
-    try:
+    run_command("Yosys", "yosys_output.txt", command)
-        with open('yosys_rewrite_veri_output.txt', 'w+') as output:
-            process = subprocess.run(command,
-                                     check=True,
-                                     stdout=subprocess.PIPE,
-                                     stderr=subprocess.PIPE,
-                                     universal_newlines=True)
-            output.write(process.stdout)
-            if process.returncode:
-                logger.info("Rewrite veri yosys run failed with returncode %d",
-                            process.returncode)
-    except Exception as e:
-        logger.exception("Failed to run VPR")
-        print(e.output)
-        clean_up_and_exit("")
-    logger.info("Yosys output is written in file yosys_rewrite_veri_output.txt")
 
 
 def run_netlists_verification():
@@ -844,8 +829,8 @@ def run_netlists_verification():
 
 def run_command(taskname, logfile, command, exit_if_fail=True):
     logger.info("Launching %s " % taskname)
-    try:
     with open(logfile, 'w+') as output:
+        try:
             output.write(" ".join(command)+"\n")
             process = subprocess.run(command,
                                      check=True,
@@ -858,8 +843,8 @@ def run_command(taskname, logfile, command, exit_if_fail=True):
                              (taskname, process.returncode))
         except (Exception, subprocess.CalledProcessError) as e:
             logger.exception("failed to execute %s" % taskname)
-        process_failed_vpr_run(e.output)
+            filter_failed_process_output(e.output)
-        print(e.output)
+            output.write(e.output)
             if exit_if_fail:
                 clean_up_and_exit("Failed to run %s task" % taskname)
             return None
@@ -867,7 +852,7 @@ def run_command(taskname, logfile, command, exit_if_fail=True):
     return process.stdout
 
 
-def process_failed_vpr_run(vpr_output):
+def filter_failed_process_output(vpr_output):
     for line in vpr_output.split("\n"):
         if "error" in line.lower():
             logger.error("-->>" + line)

openfpga_flow/scripts/run_fpga_task.py

@@ -245,7 +245,7 @@ def strip_child_logger_info(line):
         logtype, message = line.split(" - ", 1)
         lognumb = {"CRITICAL": 50, "ERROR": 40, "WARNING": 30,
                    "INFO": 20, "DEBUG": 10, "NOTSET": 0}
-        logger.log(lognumb["INFO"], message)
+        logger.log(lognumb[logtype.strip().upper()], message)
     except:
         logger.info(line)