Merge pull request #23 from RapidSilicon/qlbank_sr
QuickLogic Memory Bank Now Supports Don't Care Bits in Bitstream file
This commit is contained in:
tangxifan
GitHub
commit
95b877924a
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@ -77,6 +77,9 @@ write_fabric_bitstream
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.. note:: If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration.
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.. option:: --keep_dont_care_bits
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Keep don't care bits (``x``) in the outputted bitstream file. This is only applicable to plain text file format. If not enabled, the don't care bits are converted to either logic ``0`` or ``1``.
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.. option:: --verbose
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@ -94,6 +94,7 @@ int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx,
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CommandOptionId opt_file = cmd.option("file");
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CommandOptionId opt_file_format = cmd.option("format");
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CommandOptionId opt_fast_config = cmd.option("fast_configuration");
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CommandOptionId opt_keep_dont_care_bits = cmd.option("keep_dont_care_bits");
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/* Write fabric bitstream if required */
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int status = CMD_EXEC_SUCCESS;
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@ -125,6 +126,7 @@ int write_fabric_bitstream(const OpenfpgaContext& openfpga_ctx,
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openfpga_ctx.fabric_global_port_info(),
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cmd_context.option_value(cmd, opt_file),
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cmd_context.option_enable(cmd, opt_fast_config),
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cmd_context.option_enable(cmd, opt_keep_dont_care_bits),
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cmd_context.option_enable(cmd, opt_verbose));
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}
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@ -154,6 +154,9 @@ ShellCommandId add_openfpga_write_fabric_bitstream_command(openfpga::Shell<Openf
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/* Add an option '--fast_configuration' */
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shell_cmd.add_option("fast_configuration", false, "Reduce the size of bitstream to be downloaded");
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/* Add an option '--keep_dont_care_bit' */
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shell_cmd.add_option("keep_dont_care_bits", false, "Keep don't care bits in bitstream file; If not enabled, don't care bits are converted to logic '0' or '1'");
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/* Add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "Enable verbose output");
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@ -12,6 +12,7 @@
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#include "vtr_time.h"
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/* Headers from openfpgautil library */
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#include "openfpga_decode.h"
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#include "openfpga_digest.h"
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#include "openfpga_version.h"
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@ -192,10 +193,15 @@ static
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int write_memory_bank_flatten_fabric_bitstream_to_text_file(std::fstream& fp,
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const bool& fast_configuration,
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const bool& bit_value_to_skip,
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const FabricBitstream& fabric_bitstream) {
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const FabricBitstream& fabric_bitstream,
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const bool& keep_dont_care_bits) {
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int status = 0;
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MemoryBankFlattenFabricBitstream fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip);
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char dont_care_bit = '0';
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if (keep_dont_care_bits) {
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dont_care_bit = DONT_CARE_CHAR;
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}
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MemoryBankFlattenFabricBitstream fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip, dont_care_bit);
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/* The address sizes and data input sizes are the same across any element,
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* just get it from the 1st element to save runtime
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@ -237,10 +243,15 @@ static
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int write_memory_bank_shift_register_fabric_bitstream_to_text_file(std::fstream& fp,
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const bool& fast_configuration,
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const bool& bit_value_to_skip,
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const FabricBitstream& fabric_bitstream) {
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const FabricBitstream& fabric_bitstream,
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const bool& keep_dont_care_bits) {
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int status = 0;
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MemoryBankShiftRegisterFabricBitstream fabric_bits = build_memory_bank_shift_register_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip);
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char dont_care_bit = '0';
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if (keep_dont_care_bits) {
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dont_care_bit = DONT_CARE_CHAR;
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}
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MemoryBankShiftRegisterFabricBitstream fabric_bits = build_memory_bank_shift_register_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip, dont_care_bit);
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/* Output information about how to intepret the bitstream */
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fp << "// Bitstream word count: " << fabric_bits.num_words() << std::endl;
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@ -356,6 +367,7 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage
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const FabricGlobalPortInfo& global_ports,
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const std::string& fname,
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const bool& fast_configuration,
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const bool& keep_dont_care_bits,
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const bool& verbose) {
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/* Ensure that we have a valid file name */
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if (true == fname.empty()) {
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@ -419,13 +431,15 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage
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status = write_memory_bank_flatten_fabric_bitstream_to_text_file(fp,
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apply_fast_configuration,
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bit_value_to_skip,
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fabric_bitstream);
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fabric_bitstream,
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keep_dont_care_bits);
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} else {
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VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER == config_protocol.bl_protocol_type());
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status = write_memory_bank_shift_register_fabric_bitstream_to_text_file(fp,
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apply_fast_configuration,
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bit_value_to_skip,
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fabric_bitstream);
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fabric_bitstream,
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keep_dont_care_bits);
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}
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break;
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}
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@ -24,6 +24,7 @@ int write_fabric_bitstream_to_text_file(const BitstreamManager& bitstream_manage
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const FabricGlobalPortInfo& global_ports,
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const std::string& fname,
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const bool& fast_configuration,
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const bool& keep_dont_care_bits,
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const bool& verbose);
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} /* end namespace openfpga */
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@ -234,7 +234,8 @@ MemoryBankFabricBitstream build_memory_bank_fabric_bitstream_by_address(const Fa
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MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(const FabricBitstream& fabric_bitstream,
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const bool& fast_configuration,
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const bool& bit_value_to_skip) {
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const bool& bit_value_to_skip,
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const char& dont_care_bit) {
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/* If fast configuration is not enabled, we need all the wl address even some of them have all-zero BLs */
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if (!fast_configuration) {
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vtr::vector<FabricBitRegionId, std::map<std::string, std::string>> fabric_bits_per_region;
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@ -324,14 +325,14 @@ MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(cons
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std::vector<std::string> cur_wl_vectors;
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for (const FabricBitRegionId& region : fabric_bitstream.regions()) {
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/* If the key id is in bound for the key list in this region, find the BL and WL and add to the final bitstream database
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* If the key id is out of bound for the key list in this region, we append an all-zero string for both BL and WLs
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* If the key id is out of bound for the key list in this region, we append an all-'x' string for both BL and WLs
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*/
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if (ikey < fabric_bits_per_region_keys[region].size()) {
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cur_wl_vectors.push_back(fabric_bits_per_region_keys[region][ikey]);
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cur_bl_vectors.push_back(fabric_bits_per_region[region].at(fabric_bits_per_region_keys[region][ikey]));
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} else {
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cur_wl_vectors.push_back(std::string(max_blwl_sizes_per_region[region].second, '0'));
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cur_bl_vectors.push_back(std::string(max_blwl_sizes_per_region[region].first, '0'));
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cur_wl_vectors.push_back(std::string(max_blwl_sizes_per_region[region].second, dont_care_bit));
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cur_bl_vectors.push_back(std::string(max_blwl_sizes_per_region[region].first, dont_care_bit));
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}
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}
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/* Add the pair to std map */
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@ -398,8 +399,9 @@ std::vector<std::string> reshape_bitstream_vectors_to_first_element(const std::v
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MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_bitstream(const FabricBitstream& fabric_bitstream,
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const bool& fast_configuration,
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//const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
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const bool& bit_value_to_skip) {
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MemoryBankFlattenFabricBitstream raw_fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip);
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const bool& bit_value_to_skip,
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const char& dont_care_bit) {
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MemoryBankFlattenFabricBitstream raw_fabric_bits = build_memory_bank_flatten_fabric_bitstream(fabric_bitstream, fast_configuration, bit_value_to_skip, dont_care_bit);
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MemoryBankShiftRegisterFabricBitstream fabric_bits;
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/* Iterate over each word */
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@ -408,7 +410,7 @@ MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_b
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MemoryBankShiftRegisterFabricBitstreamWordId word_id = fabric_bits.create_word();
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std::vector<std::string> reshaped_bl_vectors = reshape_bitstream_vectors_to_first_element(bl_vec, '0');
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std::vector<std::string> reshaped_bl_vectors = reshape_bitstream_vectors_to_first_element(bl_vec, dont_care_bit);
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/* Reverse the vectors due to the shift register chain nature: first-in first-out */
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std::reverse(reshaped_bl_vectors.begin(), reshaped_bl_vectors.end());
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/* Add the BL word to final bitstream */
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@ -416,7 +418,7 @@ MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_b
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fabric_bits.add_bl_vectors(word_id, reshaped_bl_vec);
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}
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std::vector<std::string> reshaped_wl_vectors = reshape_bitstream_vectors_to_first_element(wl_vec, '0');
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std::vector<std::string> reshaped_wl_vectors = reshape_bitstream_vectors_to_first_element(wl_vec, dont_care_bit);
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/* Reverse the vectors due to the shift register chain nature: first-in first-out */
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std::reverse(reshaped_wl_vectors.begin(), reshaped_wl_vectors.end());
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/* Add the BL word to final bitstream */
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@ -63,7 +63,8 @@ size_t find_frame_based_fast_configuration_fabric_bitstream_size(const FabricBit
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*******************************************************************/
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MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(const FabricBitstream& fabric_bitstream,
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const bool& fast_configuration,
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const bool& bit_value_to_skip);
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const bool& bit_value_to_skip,
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const char& dont_care_bit = 'x');
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/********************************************************************
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* @ brief Reorganize the fabric bitstream for memory banks which use shift register to manipulate BL and WLs
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@ -96,7 +97,8 @@ MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(cons
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MemoryBankShiftRegisterFabricBitstream build_memory_bank_shift_register_fabric_bitstream(const FabricBitstream& fabric_bitstream,
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const bool& fast_configuration,
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//const std::array<MemoryBankShiftRegisterBanks, 2>& blwl_sr_banks,
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const bool& bit_value_to_skip);
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const bool& bit_value_to_skip,
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const char& dont_care_bit = 'x');
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/* Alias to a specific organization of bitstreams for memory bank configuration protocol */
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typedef std::map<std::pair<std::string, std::string>, std::vector<bool>> MemoryBankFabricBitstream;
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@ -0,0 +1,74 @@
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# Run VPR for the 'and' design
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT}
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Apply fix-up to clustering nets based on routing results
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pb_pin_fixup --verbose
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing #--verbose
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# Write the fabric hierarchy of module graph to a file
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# This is used by hierarchical PnR flows
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write_fabric_hierarchy --file ./fabric_hierarchy.txt
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# Repack the netlist to physical pbs
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# This must be done before bitstream generator and testbench generation
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# Strongly recommend it is done after all the fix-up have been applied
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repack #--verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
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# Build fabric-dependent bitstream
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build_fabric_bitstream --verbose
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# Write fabric-dependent bitstream
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write_fabric_bitstream --file fabric_bitstream.bit --format plain_text ${OPENFPGA_FAST_CONFIGURATION} --keep_dont_care_bits
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# Write the Verilog netlist for FPGA fabric
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# - Enable the use of explicit port mapping in Verilog netlist
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write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
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# Write the Verilog testbench for FPGA fabric
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# - We suggest the use of same output directory as fabric Verilog netlists
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# - Must specify the reference benchmark file if you want to output any testbenches
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# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
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# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
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# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION}
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# Write the SDC files for PnR backend
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# - Turn on every options here
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write_pnr_sdc --file ./SDC
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# Write SDC to disable timing for configure ports
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write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
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# Write the SDC to run timing analysis for a mapped FPGA fabric
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write_analysis_sdc --file ./SDC_analysis
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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@ -32,3 +32,7 @@ run-task fpga_bitstream/write_io_mapping --debug --show_thread_logs
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echo -e "Testing report bitstream distribution to file";
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run-task fpga_bitstream/report_bitstream_distribution/default_depth --debug --show_thread_logs
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run-task fpga_bitstream/report_bitstream_distribution/custom_depth --debug --show_thread_logs
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echo -e "Testing bitstream file with don't care bits";
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run-task fpga_bitstream/dont_care_bits/ql_memory_bank_flatten --debug --show_thread_logs
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run-task fpga_bitstream/dont_care_bits/ql_memory_bank_shift_register --debug --show_thread_logs
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@ -0,0 +1,44 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_dont_care_bits_example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout=
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openfpga_fast_configuration=
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
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bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
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[SYNTHESIS_PARAM]
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bench0_top = and2
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bench0_chan_width = 300
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bench1_top = or2
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bench1_chan_width = 300
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bench2_top = and2_latch
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bench2_chan_width = 300
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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end_flow_with_test=
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@ -0,0 +1,45 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_dont_care_bits_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_shift_register_sim_openfpga.xml
|
||||
|
||||
openfpga_vpr_device_layout=
|
||||
openfpga_fast_configuration=
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
|
||||
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = and2
|
||||
bench0_chan_width = 300
|
||||
|
||||
bench1_top = or2
|
||||
bench1_chan_width = 300
|
||||
|
||||
bench2_top = and2_latch
|
||||
bench2_chan_width = 300
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
end_flow_with_test=
|
||||
Loading…
Reference in New Issue